公开(公告)号：US20190214407A1

公开(公告)日：2019-07-11

申请号：US16358182

申请日：2019-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： KWANG HO LEE ,  Kwang Ho Kim ,  Seung-Hyun Cho ,  Ji Hwan Yu

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L29/423 ,  H01L27/11573 ,  H01L23/528 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11568

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/1037 ,  H01L29/4234 ,  H01L29/7889

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.

公开(公告)号：US12228461B2

公开(公告)日：2025-02-18

申请号：US17562217

申请日：2021-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Hyun Park ,  Kwang Ho Kim ,  Joo Seong Kim ,  Jun Hyeok Yang

IPC: G01K7/16 ,  G01K1/02 ,  G01K7/24 ,  G01K7/34

Abstract: A temperature sensing device including a first temperature sensor having a first resistor and a first capacitor and generating a first voltage applied to at least one of the first resistor or the first capacitor based on a first clock signal and a second clock signal generated by delaying the first clock signal, a second temperature sensor having a second resistor and a second capacitor and generating a second voltage applied to at least one of the second resistor or the second capacitor based on the first and second clock signals, a controller generating code data based on the first voltage and the second voltage and generating a control signal based on the code data, and a delay locked loop circuit delaying the first clock signal based on the control signal to generate the second clock signal may be provided.

公开(公告)号：US10712762B2

公开(公告)日：2020-07-14

申请号：US16447259

申请日：2019-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo Seong Kim ,  Kwang Ho Kim ,  Sang Ho Kim

IPC: G05F3/26

Abstract: Provided are a semiconductor circuit and a semiconductor system. A semiconductor circuit includes a bandgap reference voltage generation circuit including an operational amplifier to amplify a differential voltage between a first node and a second node; a first startup circuit which receives input of an output signal of the operational amplifier from an output voltage node of the bandgap reference voltage generation circuit and pulls up the second node; and a second startup circuit which pulls down the output voltage node.

公开(公告)号：US10068860B2

公开(公告)日：2018-09-04

申请号：US15010520

申请日：2016-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Ho Kim ,  Sang Ho Kim

IPC: G06K19/073 ,  G06K7/10 ,  H01L27/14 ,  H01L23/00 ,  H01L31/00 ,  H01L31/02 ,  G06F21/70

Abstract: A laser detector includes a latch and a semiconductor device including the same. The laser detector includes a latch configured to output an output signal and an inverted output signal and an initial value setting circuit configured to set an initial value of at least one of the output signal and the inverted output signal. The latch includes a first transistor controlled to be initially turned on by the initial value and a second transistor controlled to be initially turned off by the initial value. The second transistor has an active region having a lateral area that is greater than that of the first transistor.

公开(公告)号：US10276591B2

公开(公告)日：2019-04-30

申请号：US15937932

申请日：2018-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang Ho Lee ,  Kwang Ho Kim ,  Seung Hynu Cho ,  Ji Hwan Yu

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/11568 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/788 ,  H01L29/10

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.