公开(公告)号：US20210399005A1

公开(公告)日：2021-12-23

申请号：US17220340

申请日：2021-04-01

申请人： Samsung Electronics Co., Ltd.

发明人： Sooyong Lee ,  Seorim Moon ,  Bongsoo Kang ,  Kyungjae Park ,  Cheol Ryou

IPC分类号： H01L27/11575 ,  H01L23/535 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

摘要： A semiconductor device includes a peripheral circuit region including a first substrate and circuit devices on the first substrate, a memory cell region including a second substrate on the first substrate, a horizontal conductive layer on the second substrate, gate electrodes stacked on the horizontal conductive layer in a first direction perpendicular to an upper surface of the second substrate and spaced apart from each other, and channel structures extending in gate electrodes in the first direction, each of the channel structures including a channel layer in physical contact with the horizontal conductive layer, and a through wiring region including a through contact plug extending in the first direction and electrically connecting the memory cell region to the peripheral circuit region, an insulating region bordering the through contact plug, and dummy channel structures partially extending into the insulating region in the first direction.

公开(公告)号：US11889700B2

公开(公告)日：2024-01-30

申请号：US17220340

申请日：2021-04-01

申请人： Samsung Electronics Co., Ltd.

发明人： Sooyong Lee ,  Seorim Moon ,  Bongsoo Kang ,  Kyungjae Park ,  Cheol Ryou

IPC分类号： H10B43/50 ,  H01L23/535 ,  H01L21/768 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

CPC分类号： H10B43/50 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

摘要： A semiconductor device includes a peripheral circuit region including a first substrate and circuit devices on the first substrate, a memory cell region including a second substrate on the first substrate, a horizontal conductive layer on the second substrate, gate electrodes stacked on the horizontal conductive layer in a first direction perpendicular to an upper surface of the second substrate and spaced apart from each other, and channel structures extending in gate electrodes in the first direction, each of the channel structures including a channel layer in physical contact with the horizontal conductive layer, and a through wiring region including a through contact plug extending in the first direction and electrically connecting the memory cell region to the peripheral circuit region, an insulating region bordering the through contact plug, and dummy channel structures partially extending into the insulating region in the first direction.

公开(公告)号：US12010840B2

公开(公告)日：2024-06-11

申请号：US17013726

申请日：2020-09-07

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Leeeun Ku ,  Yuna Lee ,  Sunyoung Kim ,  Kyungjae Park ,  Jonghyun Park ,  Bora Lee ,  Jongho Lim

IPC分类号： H01L27/115 ,  H01L23/522 ,  H10B43/10 ,  H10B43/27

CPC分类号： H10B43/27 ,  H01L23/5226 ,  H10B43/10

摘要： A vertical type non-volatile memory device includes a substrate having a cell array area of a block unit and an extension area, a vertical contact disposed in the extension area, a plurality of vertical channel structures provided on the substrate in the cell array area, a plurality of dummy channel structures provided on the substrate in the extension area, and a plurality of gate electrode layers and a plurality of interlayer insulation layers stacked alternately on the substrate. In an electrode pad connected to the vertical contact, dummy channel structures are disposed at both sides of the vertical contact and a horizontal cross-sectional surface of each of the plurality of dummy channel structures has a shape which is longer in one direction.