公开(公告)号：US20170329889A1

公开(公告)日：2017-11-16

申请号：US15443195

申请日：2017-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MOO-KYUNG LEE ,  JAEICK SON ,  SUNGHOON KIM

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F2217/06 ,  G06F2217/12

Abstract: An integrated circuit of a semiconductor device is fabricated by forming patterns on a wafer in conformance with a layout of the patterns. A method for verifying the layout includes providing a virtual pattern on a predicted defect point in the layout, and identifying at least one pattern from among those of the layout using the virtual pattern. The predicted defect point corresponds to a weak point where it is determined in advance that a defect will occur when the layout is transcribed on a wafer. The identified pattern is a pattern that is adjacent to the virtual pattern in the layout.