公开(公告)号：US20250048727A1

公开(公告)日：2025-02-06

申请号：US18611960

申请日：2024-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHANGHUN KIM ,  JAEICK SON

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a first substrate doped with an impurity of a first conductivity-type, a first well region formed in the first substrate and doped with an impurity of a second conductivity-type, different from the first conductivity-type, a first guard band that extends in a first direction, parallel to an upper surface of the substrate, is in the first well region, and doped with an impurity of the second conductivity-type, a second guard band facing the first guard band, in the substrate, and doped with an impurity of the first conductivity-type, a first electrode structure electrically connected to the first guard band, a second electrode structure electrically connected to the second guard band, and a first insulating layer on sidewalls of the first electrode structure and the second electrode structure, the first electrode structure, the insulating layer, and the second electrode structure provide a capacitor.

公开(公告)号：US20240038603A1

公开(公告)日：2024-02-01

申请号：US18103747

申请日：2023-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunhaeng Heo ,  SUNGHOON KIM ,  JAEICK SON ,  SEUNGYEON KIM

IPC: H01L21/66 ,  H10B80/00

CPC classification number: H01L22/32 ,  H10B80/00

Abstract: A semiconductor chip including a guard ring that surrounds edges of a semiconductor substrate, an internal circuit structure that is formed on the semiconductor substrate and that includes a memory cell array region and a peripheral circuit region, and a crack detection circuit that is located between the guard ring and the internal circuit structure and that detects whether a crack occurs. The semiconductor chip further includes first to fourth chamfer regions having different shapes and sizes depending on the position of a pad or the design arrangement of the internal circuit structure.

公开(公告)号：US20170329889A1

公开(公告)日：2017-11-16

申请号：US15443195

申请日：2017-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MOO-KYUNG LEE ,  JAEICK SON ,  SUNGHOON KIM

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F2217/06 ,  G06F2217/12

Abstract: An integrated circuit of a semiconductor device is fabricated by forming patterns on a wafer in conformance with a layout of the patterns. A method for verifying the layout includes providing a virtual pattern on a predicted defect point in the layout, and identifying at least one pattern from among those of the layout using the virtual pattern. The predicted defect point corresponds to a weak point where it is determined in advance that a defect will occur when the layout is transcribed on a wafer. The identified pattern is a pattern that is adjacent to the virtual pattern in the layout.