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    SEMICONDUCTOR CHIP HAVING CHAMFER REGION FOR CRACK PREVENTION
    1.
    发明公开
    SEMICONDUCTOR CHIP HAVING CHAMFER REGION FOR CRACK PREVENTION 审中-公开

    公开(公告)号：US20240038603A1

    公开(公告)日：2024-02-01

    申请号：US18103747

    申请日：2023-01-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunhaeng Heo ,  SUNGHOON KIM ,  JAEICK SON ,  SEUNGYEON KIM

    IPC: H01L21/66 ,  H10B80/00

    CPC classification number: H01L22/32 ,  H10B80/00

    Abstract: A semiconductor chip including a guard ring that surrounds edges of a semiconductor substrate, an internal circuit structure that is formed on the semiconductor substrate and that includes a memory cell array region and a peripheral circuit region, and a crack detection circuit that is located between the guard ring and the internal circuit structure and that detects whether a crack occurs. The semiconductor chip further includes first to fourth chamfer regions having different shapes and sizes depending on the position of a pad or the design arrangement of the internal circuit structure.

    INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAME
    5.
    发明申请
    INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAME 有权

    公开(公告)号：US20220122967A1

    公开(公告)日：2022-04-21

    申请号：US17224558

    申请日：2021-04-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： CHANG-BUM KIM ,  SUNGHOON KIM ,  DAESEOK BYEON

    IPC: H01L27/07 ,  H01L29/06

    Abstract: An integrated circuit includes; a substrate including a single active region, a first active resistor formed on the substrate, and a transistor including a first junction area in the single active region. The first active resistor and the transistor are electrically connected through the first junction area. The first active resistor is formed between a first node and a second node included in the first junction area. The first node is connected to a first contact, and the second node is connected to a second contact.

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220173100A1

    公开(公告)日：2022-06-02

    申请号：US17536413

    申请日：2021-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： AHREUM KIM ,  SUNGHOON KIM ,  DAESEOK BYEON

    IPC: H01L27/092

    Abstract: A semiconductor device includes a substrate, an N-well area formed in the substrate, a first P-channel metal oxide semiconductor (PMOS) transistor having active regions formed in the N-well area, and a first N-channel metal oxide semiconductor (NMOS) transistor having active regions formed in the substrate. The first NMOS transistor includes a first N-type active region overlapping each of the substrate and the N-well area, when viewed from above a plane parallel to a top surface of the substrate.

    3-DIMENSIONAL MEMORY DEVICE
    9.
    发明申请
    3-DIMENSIONAL MEMORY DEVICE 审中-公开

    公开(公告)号：US20200381037A1

    公开(公告)日：2020-12-03

    申请号：US16840596

    申请日：2020-04-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： CHANGBUM KIM ,  SUNGHOON KIM ,  SEUNGYEON KIM

    IPC: G11C11/408 ,  G11C11/4099 ,  G11C5/02 ,  H01L27/24

    Abstract: A memory device including a first memory cell array including first memory cells stacked vertically on a first memory cell array region of a top surface of a substrate; a second memory cell array including second memory cells stacked vertically on a second memory cell array region of the top surface; first word lines coupled to the first memory cells and including a subset of first word lines and remaining first word lines; second word lines coupled to the second memory cells and including a subset of second word lines and remaining second word lines; and a row decoder, including a plurality of merge pass transistors each commonly connected to a respective one of the subset of first word lines and a respective one of the subset of second word lines, disposed in a region of the top surface between the first and second cell array regions.

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