公开(公告)号：US20230143829A1

公开(公告)日：2023-05-11

申请号：US17965004

申请日：2022-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Min-Hwi Kim ,  Makoto Hirano

IPC: G11C16/24 ,  G06F12/0802

CPC classification number: G11C16/24 ,  G06F12/0802 ,  G11C16/0483

Abstract: A memory device includes a memory cell array and a page buffer circuit, wherein the page buffer circuit includes page buffer units including upper page buffer units and lower page buffer units and cache units arranged between the upper page buffer unit and the lower page buffer units. The cache units include upper cache units and lower cache units. Each page buffer unit includes a sensing node and a pass transistor. The upper cache units share a first combined sensing node, and, the lower cache units share a second combined sensing node. In a data transmission period, sensing nodes respectively included the page buffer units are electrically connected to one another through serial connections of the pass transistors respectively included in the page buffer units.

公开(公告)号：US20240105267A1

公开(公告)日：2024-03-28

申请号：US18201331

申请日：2023-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inho Kang ,  Daeseok Byeon ,  Beakhyung Cho ,  Min-Hwi Kim ,  Yongsung Cho ,  Gyosoo Choo

IPC: G11C16/24 ,  G11C16/04 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/41 ,  H10B43/40 ,  H10B80/00

CPC classification number: G11C16/24 ,  G11C16/0483 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/41 ,  H10B43/40 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: Provided is a non-volatile memory device including a page buffer circuit having a multi-stage structure, wherein a stage of the multi-stage structure includes a high voltage region, a first low voltage region, and a second low voltage region. The high voltage region includes a first high voltage transistor connected to one of first to sixth bit lines and a second high voltage transistor connected to one of seventh to twelfth bit lines, the first low voltage region includes a first transistor connected to the first high voltage transistor, and the second low voltage region includes a second transistor connected to the second high voltage transistor. Each of the first low voltage region and the second low voltage regions has a first width corresponding to a pitch of six bit lines, and the high voltage region has a second width corresponding to a pitch of twelve bit lines.

公开(公告)号：US12217804B2

公开(公告)日：2025-02-04

申请号：US17960630

申请日：2022-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Min-Hwi Kim ,  Hosang Cho

IPC: G11C16/26 ,  G11C16/04

Abstract: A cache read method of a nonvolatile memory device including a plurality of page buffer units and cache latches, each page buffer units having a sensing latch and a sensing node line is provided. The method comprises performing a first on-chip valley search (OVS) read on a selected memory cell using a first sensing node line and a first sensing latch of a first page buffer unit of the plurality of page buffer units; storing first data sensed from the selected memory cell in the first sensing latch, the first data based on a result of the first OVS read; dumping the first data to sensing node lines of at least one page buffer unit, excluding the first page buffer unit, from among the plurality of page buffer units; and performing a second OVS read on the selected memory cell using the first sensing latch.

公开(公告)号：US12211559B2

公开(公告)日：2025-01-28

申请号：US17965004

申请日：2022-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Min-Hwi Kim ,  Makoto Hirano

IPC: G11C16/24 ,  G06F12/0802 ,  G11C16/04 ,  H10B43/27

Abstract: A memory device includes a memory cell array and a page buffer circuit, wherein the page buffer circuit includes page buffer units including upper page buffer units and lower page buffer units and cache units arranged between the upper page buffer unit and the lower page buffer units. The cache units include upper cache units and lower cache units. Each page buffer unit includes a sensing node and a pass transistor. The upper cache units share a first combined sensing node, and, the lower cache units share a second combined sensing node. In a data transmission period, sensing nodes respectively included the page buffer units are electrically connected to one another through serial connections of the pass transistors respectively included in the page buffer units.