公开(公告)号：US20180374869A1

公开(公告)日：2018-12-27

申请号：US15993756

申请日：2018-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-soo KIM ,  Yong-seok KIM ,  Tae-hun KIM ,  Min-kyung BAE ,  Jae-hoon JANG ,  Kohji KANAMORI

IPC: H01L27/11582 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L29/0847 ,  H01L29/7827

Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.

公开(公告)号：US20190355744A1

公开(公告)日：2019-11-21

申请号：US16526139

申请日：2019-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-soo KIM ,  Yong-seok KIM ,  Tae-hun KIM ,  Min-kyung BAE ,  Jae-hoon JANG ,  Kohji KANAMORI

IPC: H01L27/11582 ,  H01L29/08 ,  H01L29/78

Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.