公开(公告)号：US11640922B2

公开(公告)日：2023-05-02

申请号：US17578785

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miso Shin ,  Chungki Min ,  Gihwan Kim ,  Sanghyeok Kim ,  Hyo-Jung Kim ,  Geunwon Lim

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/3105 ,  H01L27/11573 ,  H01L21/324 ,  H01L27/11582 ,  H01L21/311

Abstract: A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.

公开(公告)号：US10916554B2

公开(公告)日：2021-02-09

申请号：US16793301

申请日：2020-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Miso Shin ,  Myeongan Kwon ,  Chungki Min ,  Byoungho Kwon ,  Boun Yoon

IPC: H01L27/11548 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.

公开(公告)号：US11257708B2

公开(公告)日：2022-02-22

申请号：US16377516

申请日：2019-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miso Shin ,  Chungki Min ,  Gihwan Kim ,  Sanghyeok Kim ,  Hyo-Jung Kim ,  Geunwon Lim

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/3105 ,  H01L27/11573 ,  H01L21/324 ,  H01L27/11582 ,  H01L21/311

Abstract: A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.

公开(公告)号：US10566338B2

公开(公告)日：2020-02-18

申请号：US15922186

申请日：2018-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Miso Shin ,  Myeongan Kwon ,  Chungki Min ,  Byoungho Kwon ,  Boun Yoon

IPC: H01L27/11548 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.