公开(公告)号：US20230371254A1

公开(公告)日：2023-11-16

申请号：US18062169

申请日：2022-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon KWON ,  Hyo-Jung Kim ,  Chungki Min ,  Boun Yoon

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

Abstract: A semiconductor device may include a gate stack including insulating patterns and conductive patterns, which are alternately stacked, first block channel structures penetrating the gate stack, second block channel structures penetrating the gate stack, and an isolation structure penetrating the gate stack. The isolation structure may include a block isolation structure, a first word line isolation structure, and a second word line isolation structure. The block isolation structure may include a first side surface connected to a side surface of the first word line isolation structure, and a second side surface connected to a side surface of the second word line isolation structure, and the first block channel structures comprise an intervening channel structure between the first and second side surfaces of the block isolation structure.

公开(公告)号：US20150200259A1

公开(公告)日：2015-07-16

申请号：US14474336

申请日：2014-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Heun Lim ,  Myung-Jung Pyo ,  Kyung-Hyun Kim ,  Dong-Sik Kim ,  Hyo-Jung Kim

IPC: H01L29/36 ,  H01L27/115 ,  H01L21/225 ,  H01L29/792

CPC classification number: H01L29/36 ,  H01L21/2253 ,  H01L21/26513 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7926

Abstract: A method of manufacturing a vertical-cell-type semiconductor device may include stacking alternately first insulating layers and second insulating layers on a substrate, forming a channel hole through the first and second insulating layers, and forming dielectric layers. A channel layer and a gap fill pattern may be formed within the channel hole. The channel layer may cover a top surface of an uppermost first insulating layer. The top surface of the gap fill pattern is at the same level with the top surface of the channel layer. A first conductivity type impurities may be implanted into the channel layer to form a channel impurity region. A top surface of the gap fill pattern may be recessed. A contact pad on the recessed surface of the gap fill pattern may be formed. A ground selection gate electrode, cell gate electrodes, and string selection gate electrodes may be formed in interlayer spaces that be formed by removing the second insulating layers. String selection gate electrodes may formed in the channel impurity region.

Abstract translation: 制造垂直单元型半导体器件的方法可以包括在衬底上交替地堆叠第一绝缘层和第二绝缘层，形成通过第一和第二绝缘层的沟道孔，并形成电介质层。 可以在通道孔内形成通道层和间隙填充图案。 沟道层可以覆盖最上面的第一绝缘层的顶表面。 间隙填充图案的顶表面与通道层的顶表面处于同一水平。 可以将第一导电类型的杂质注入到沟道层中以形成沟道杂质区。 间隙填充图案的顶表面可以凹入。 可以形成间隙填充图案的凹陷表面上的接触垫。 可以在通过去除第二绝缘层形成的层间空间中形成接地选择栅电极，单元栅电极和串选择栅电极。 串选择栅电极可以形成在沟道杂质区中。

公开(公告)号：US08877634B2

公开(公告)日：2014-11-04

申请号：US13720170

申请日：2012-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Woon Shin ,  Bong-Hyun Kim ,  Su-Min Kim ,  Hyo-Jung Kim ,  Chang-Min Park ,  Soo-Jin Hong

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/308 ,  H01L21/033 ,  H01L27/108 ,  H01L21/311

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

Abstract: The inventive concept provides methods of manufacturing semiconductor devices having a fine pattern. In some embodiments, the methods comprise forming an etch-target film on a substrate, forming a first mask pattern on the etch-target film, forming a second mask pattern by performing an ion implantation process in the first mask pattern, and etching the etch-target film using the second mask pattern.

Abstract translation: 本发明构思提供制造具有精细图案的半导体器件的方法。 在一些实施例中，所述方法包括在衬底上形成蚀刻靶膜，在蚀刻靶膜上形成第一掩模图案，通过在第一掩模图案中执行离子注入工艺形成第二掩模图案，并蚀刻蚀刻 - 使用第二掩模图案的目标膜。

公开(公告)号：US11257708B2

公开(公告)日：2022-02-22

申请号：US16377516

申请日：2019-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miso Shin ,  Chungki Min ,  Gihwan Kim ,  Sanghyeok Kim ,  Hyo-Jung Kim ,  Geunwon Lim

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/3105 ,  H01L27/11573 ,  H01L21/324 ,  H01L27/11582 ,  H01L21/311

Abstract: A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.

公开(公告)号：US10334173B2

公开(公告)日：2019-06-25

申请号：US15343767

申请日：2016-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Tae Jin ,  So-Yeon Kim ,  Hyo-Jung Kim ,  Dae-Woong Song ,  Soo-Jung Lee ,  Eo-Jin Lim ,  Seong-Yeon Hwang

IPC: H04N5/232 ,  H04N1/00 ,  G06T11/00 ,  G06T11/60

Abstract: An electronic device is provided. The electronic device includes a storage configured to store information about a plurality of color assignment areas included in an image editing tool displayed on a screen of the electronic device, a display configured to display the image editing tool including the plurality of color assignment areas on the screen of the electronic device, and a controller configured to run a preset application installed in the electronic device in response to an input related to color extraction, and display a color selected in at least one area of an execution screen of the application in the color assignment areas of the image editing tool.

公开(公告)号：US20130267092A1

公开(公告)日：2013-10-10

申请号：US13720170

申请日：2012-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Woon Shin ,  Bong-Hyun Kim ,  Su-Min Kim ,  Hyo-Jung Kim ,  Chang-Min Park ,  Soo-Jin Hong

IPC: H01L21/308 ,  H01L21/768

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

Abstract: The inventive concept provides methods of manufacturing semiconductor devices having a fine pattern. In some embodiments, the methods comprise forming an etch-target film on a substrate, forming a first mask pattern on the etch-target film, forming a second mask pattern by performing an ion implantation process in the first mask pattern, and etching the etch-target film using the second mask pattern.

Abstract translation: 本发明构思提供制造具有精细图案的半导体器件的方法。 在一些实施例中，所述方法包括在衬底上形成蚀刻靶膜，在蚀刻靶膜上形成第一掩模图案，通过在第一掩模图案中执行离子注入工艺形成第二掩模图案，并蚀刻蚀刻 - 使用第二掩模图案的目标膜。

公开(公告)号：US11640922B2

公开(公告)日：2023-05-02

申请号：US17578785

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miso Shin ,  Chungki Min ,  Gihwan Kim ,  Sanghyeok Kim ,  Hyo-Jung Kim ,  Geunwon Lim

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/3105 ,  H01L27/11573 ,  H01L21/324 ,  H01L27/11582 ,  H01L21/311

Abstract: A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.

公开(公告)号：US20240298441A1

公开(公告)日：2024-09-05

申请号：US18476415

申请日：2023-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-Jung Kim ,  Donghoon Kwon

IPC: H10B41/41 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B41/41 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device may include a peripheral circuit structure, a source structure on the peripheral circuit structure, a first capacitor electrode on the peripheral circuit structure, an electrode insulating layer that at least partially surrounds the first capacitor electrode, a gate stack on the source structure, a memory channel structure that extends through the gate stack, a staircase insulating layer on the gate stack and the electrode insulating layer, a second capacitor electrode on the first capacitor electrode and that extends through the staircase insulating layer, and a penetration via that extends through the staircase insulating layer and the electrode insulating layer.

公开(公告)号：US09502332B2

公开(公告)日：2016-11-22

申请号：US13927914

申请日：2013-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Heun Lim ,  Hyo-Jung Kim ,  Ji-Woon Im ,  Kyung-Hyun Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/115

CPC classification number: H01L23/48 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes, a first recess formed in the electrode structure on the connection region and disposed between the cell array region and a second recess formed in the electrode structure on the connection region, and a plurality of vertical wirings formed on the plurality of electrodes exposed by the first recess.

Abstract translation: 一种非易失性存储器件，包括：包括单元阵列区域和连接区域的基板;形成在单元阵列区域上的电极结构和连接区域，并且包括多个层压电极;形成在电极结构中的第一凹部， 并且布置在单元阵列区域和形成在连接区域上的电极结构中的第二凹槽之间，以及形成在由第一凹部暴露的多个电极上的多个垂直布线。