公开(公告)号：US20230286108A1

公开(公告)日：2023-09-14

申请号：US17931948

申请日：2022-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon Kwon ,  Hyojung Kim ,  Chungki Min ,  Kihoon Jang

IPC: B24B55/02 ,  B24B57/02 ,  B24B37/10 ,  B24B37/34 ,  B24B53/017

CPC classification number: B24B55/02 ,  B24B57/02 ,  B24B37/107 ,  B24B37/34 ,  B24B53/017

Abstract: A polishing apparatus for a substrate, includes: a platen having a polishing pad attached to an upper surface thereof, and configured to rotate in a rotational direction, a temperature control unit configured to spray a temperature control fluid onto the polishing pad, a slurry supply unit configured to supply a slurry to the polishing pad, a polishing head on the polishing pad, and configured to rotate a semiconductor substrate in contact with the polishing pad, and a first fence between the temperature control unit and the slurry supply unit extending from a center outwardly, along the rotational direction, to control a flow of the temperature control fluid, wherein the temperature control unit, the slurry supply unit, and the polishing head are sequentially positioned along the rotational direction.

公开(公告)号：US20240217057A1

公开(公告)日：2024-07-04

申请号：US18347707

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon Kwon ,  Chungki Min

IPC: B24B37/26

CPC classification number: B24B37/26

Abstract: The present disclosure relates to a chemical mechanical polishing apparatus and a method of replacing a polishing pad using the same. The chemical mechanical polishing apparatus includes: a polishing table; a polishing pad attachment feature on a surface of the polishing table; a polishing pad supply area outside the polishing table; and a polishing pad carrier configured to move a polishing pad from the polishing pad supply area to the polishing pad attachment feature, wherein the polishing pad attachment feature includes a magnetic feature and/or an adsorption feature to attach the polishing pad to the polishing table.

公开(公告)号：US11640922B2

公开(公告)日：2023-05-02

申请号：US17578785

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miso Shin ,  Chungki Min ,  Gihwan Kim ,  Sanghyeok Kim ,  Hyo-Jung Kim ,  Geunwon Lim

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/3105 ,  H01L27/11573 ,  H01L21/324 ,  H01L27/11582 ,  H01L21/311

Abstract: A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.

公开(公告)号：US10916554B2

公开(公告)日：2021-02-09

申请号：US16793301

申请日：2020-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Miso Shin ,  Myeongan Kwon ,  Chungki Min ,  Byoungho Kwon ,  Boun Yoon

IPC: H01L27/11548 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.

公开(公告)号：US20230371254A1

公开(公告)日：2023-11-16

申请号：US18062169

申请日：2022-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon KWON ,  Hyo-Jung Kim ,  Chungki Min ,  Boun Yoon

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

Abstract: A semiconductor device may include a gate stack including insulating patterns and conductive patterns, which are alternately stacked, first block channel structures penetrating the gate stack, second block channel structures penetrating the gate stack, and an isolation structure penetrating the gate stack. The isolation structure may include a block isolation structure, a first word line isolation structure, and a second word line isolation structure. The block isolation structure may include a first side surface connected to a side surface of the first word line isolation structure, and a second side surface connected to a side surface of the second word line isolation structure, and the first block channel structures comprise an intervening channel structure between the first and second side surfaces of the block isolation structure.

公开(公告)号：US11744079B2

公开(公告)日：2023-08-29

申请号：US17473141

申请日：2021-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon Kwon ,  Chang-Sun Hwang ,  Chungki Min

IPC: H01L23/535 ,  H10B43/50 ,  H01L23/00 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H01L23/535 ,  H01L23/562 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes an upper-level layer having a cell array region, a cell contact region and a dummy region on a substrate. The upper-level layer includes a semiconductor layer, a cell array structure including first and second stack structures sequentially stacked on the semiconductor layer of the cell array region, the first and second stack structures comprising stacked electrodes, a first staircase structure on the semiconductor layer of the cell contact region, the electrodes extending from the cell array structure into the first staircase structure such that the cell array structure is connected to the first staircase structure, a vertical channel structure penetrating the cell array structure, a dummy structure in the dummy region, the dummy structure at the same level as the second stack structure, the dummy structure including stacked first layers, and cell contact plugs in the cell contact region and connected to the first staircase structure.

公开(公告)号：US11417675B2

公开(公告)日：2022-08-16

申请号：US16903514

申请日：2020-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Jang ,  Chang-Sun Hwang ,  Chungki Min ,  Kieun Seo ,  Jongheun Lim

IPC: H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L21/768 ,  H01L27/11582 ,  H01L23/535 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device including a peripheral circuit structure on a first substrate, the peripheral circuit structure including peripheral circuits, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure including a plurality of electrodes that are stacked on the second substrate and a penetrating interconnection structure penetrating the electrode structure and the second substrate may be provided. The penetrating interconnection structure may include a lower insulating pattern, a mold pattern structure on the lower insulating pattern, a protection pattern between the lower insulating pattern and the mold pattern structure, and a penetration plug. The penetration plug may penetrate the mold pattern structure and the lower insulating pattern and may be connected to the peripheral circuit structure. The protection pattern may be at a level lower than that of the lowermost one of the electrodes.

公开(公告)号：US12089407B2

公开(公告)日：2024-09-10

申请号：US17574740

申请日：2022-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghoon Kwon ,  Chungki Min

IPC: H10B43/27 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor device includes a peripheral circuit structure including a lower substrate, a plurality of circuits formed on the lower substrate, and a plurality of wiring layers connected to the plurality of circuits, an upper substrate covering the peripheral circuit structure and including a through opening, a memory stack structure including a plurality of gate lines, a memory cell contact passing through at least one of the plurality of gate lines to contact one gate line from among the plurality of gate lines, the memory cell contact extending to the peripheral circuit structure through the through opening and being configured to be electrically connected to a first wiring layer from among the plurality of wiring layers, and a plurality of dummy channel structures passing through at least one of the plurality of gate lines to extend to the peripheral circuit structure through the through opening.

公开(公告)号：US11889688B2

公开(公告)日：2024-01-30

申请号：US17509567

申请日：2021-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Sun Hwang ,  Gihwan Kim ,  Chungki Min

IPC: H01L27/11556 ,  H10B41/27 ,  H01L29/66 ,  G11C5/02 ,  H01L25/07 ,  G11C5/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L25/074 ,  H01L29/66666 ,  H10B43/27

Abstract: A semiconductor device include; a substrate including a cell array region and a key region, a stack structure on the cell array region including vertically stacked electrodes, a dummy structure on the key region, a vertical channel structure penetrating the stack structure to connect the substrate, a dummy pillar penetrating the first dummy structure, an interlayer dielectric layer on the stack structure and the dummy structure, wherein an upper portion of the interlayer dielectric layer on the dummy structure includes a key pattern that vertically overlaps the dummy pillar, and a capping layer on the key region and covering the key pattern.

公开(公告)号：US20230097021A1

公开(公告)日：2023-03-30

申请号：US17828339

申请日：2022-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon Kwon ,  Chungki Min ,  Kihoon Jang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/48 ,  G11C5/06

Abstract: A semiconductor device includes: a first substrate; a second substrate including first and second regions; a stack structure in the first region and extending from the first region into the second region, the stack structure including interlayer insulating layers and gate layers, wherein the gate layers include gate pads having a step shape in the second region; a capping insulating layer at least partially covering the stack structure; an upper insulating layer on the stack structure and the capping insulating layer; a peripheral contact structure including a plurality of through-vias contacting the second substrate and spaced apart from the gate layers, and a peripheral contact pattern on the plurality of through-vias and connecting at least a portion of the plurality of through-vias to each other; a memory vertical structure; a support vertical structure; and a gate contact plug on the gate pads to be electrically connected to the gate pads.