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    Memory controller, memory system including the same, and method of operating the same
    3.
    发明授权
    Memory controller, memory system including the same, and method of operating the same 有权

    公开(公告)号：US11675504B2

    公开(公告)日：2023-06-13

    申请号：US17224573

    申请日：2021-04-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myeongjong Ju ,  Seungjae Lee ,  Jisoo Kim

    IPC: G06F3/06

    CPC classification number: G06F3/0623 ,  G06F3/0655 ,  G06F3/0679

    Abstract: A memory controller includes a key generator, an encryption and decryption circuit, and a processor. The key generator generates a first security key and a second security key based on a write request from a host. The encryption and decryption circuit encrypts write data corresponding to the write request based on the first security key to generate encrypted write data, and encrypts the first security key based on the second security key to generate a first encrypted security key. The processor controls nonvolatile memories such that the encrypted write data, the first encrypted security key, and the second security key are programmed in at least one of the nonvolatile memories, and controls the nonvolatile memories such that a dummy program operation is performed on a page of the nonvolatile memories in which the second security key is programmed instead of erasing the encrypted write data.

    MEMORY DEVICE, OPERATING METHOD OF THE SAME, AND MEMORY SYSTEM
    8.
    发明公开
    MEMORY DEVICE, OPERATING METHOD OF THE SAME, AND MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240202361A1

    公开(公告)日：2024-06-20

    申请号：US18539799

    申请日：2023-12-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yongsuk Lee ,  Myeongjong Ju ,  Jisoo Kim

    IPC: G06F21/62 ,  G06F21/60

    CPC classification number: G06F21/6245 ,  G06F21/602

    Abstract: A memory device includes one or more non-volatile memories configured to store user data and at least one key related to the user data; a network-on-chip comprising a bus manager configured to manage access to the user data and the at least one key; and a debug port directly connected to a host and configured to receive a request from the host, wherein the bus manager is further configured to, based on the debug port being activated, determine whether to allow access of the host to the user data and the at least one key based on classification information.

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