公开(公告)号：US20230214138A1

公开(公告)日：2023-07-06

申请号：US17748564

申请日：2022-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Raghu Vamsi Krishna TALANKI ,  Archita KHARE ,  Rahul Tarikere RAVIKUMAR ,  Jinin SO ,  Jonggeon LEE

IPC: G06F3/06 ,  G06F12/1027

CPC classification number: G06F3/0632 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/1027

Abstract: A memory interface for interfacing with a memory device includes a control circuit configured to determine whether a trigger event has occurred for initializing one or more memory locations in the memory device, and initialize the one or more memory locations in the memory device with pre-defined data upon determining the trigger event has occurred.

公开(公告)号：US20240295963A1

公开(公告)日：2024-09-05

申请号：US18310741

申请日：2023-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raghu Vamsi Krishna TALANKI ,  Archita KHARE ,  Eldho P. MATHEW ,  Jin In SO ,  Jong-Geon LEE ,  Venkata Ravi Shankar JONNALAGADDA ,  Vishnu Charan THUMMALA

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673

Abstract: The present disclosure relates to field of Dual In-Line Memory Modules that discloses method and system for generating memory maps. The method comprises detecting, by computing system, at least one of DIMM and one or more Dynamic Random Access Memory (DRAM) chips associated with computing system. The one or more accelerators are configured in at least one of DIMM and one or more DRAM chips. Further, the method includes determining accelerator information for each of one or more accelerators via at least one of Serial Presence Detect (SPD) and Multi-Purpose Register (MPR) associated with at least one of DIMM and one or more DRAM chips. Method includes generating unique memory map for each of one or more accelerators based on accelerator information of corresponding one or more accelerators. As a result, performance of computing system may be improved as accelerator capabilities of one or more accelerators are effectively utilized.

公开(公告)号：US20230004489A1

公开(公告)日：2023-01-05

申请号：US17854772

申请日：2022-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Raghu Vamsi Krishna TALANKI ,  Eldho Pathiyakkara Thombra Mathew ,  Vishnu Charan Thummala ,  Vinod Kumar Srinivasan ,  Jin ln So ,  Jong-Geon Lee

IPC: G06F12/06

Abstract: A Near Memory Processing (NMP) dual in-line memory module (DIMM) for managing an address map is provided. The NMP DIMM includes: a static random-access memory (SRAM) provided on a Double Data Rate (DDR) interface; and an address management controller coupled to the SRAM, and configured to control the NMP DIMM to: receive a first indication from a host system to perform interface training for operating an SRAM space; perform the interface training using a first address map based on the first indication; receive a second indication from the host system indicating completion of the interface training for operating the SRAM space; switch from the first address map to a second address map for operating the SRAM space in response based on the second indication; and operate the SRAM space using the second address map.