公开(公告)号：US20230214138A1

公开(公告)日：2023-07-06

申请号：US17748564

申请日：2022-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Raghu Vamsi Krishna TALANKI ,  Archita KHARE ,  Rahul Tarikere RAVIKUMAR ,  Jinin SO ,  Jonggeon LEE

IPC: G06F3/06 ,  G06F12/1027

CPC classification number: G06F3/0632 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/1027

Abstract: A memory interface for interfacing with a memory device includes a control circuit configured to determine whether a trigger event has occurred for initializing one or more memory locations in the memory device, and initialize the one or more memory locations in the memory device with pre-defined data upon determining the trigger event has occurred.

公开(公告)号：US20220206968A1

公开(公告)日：2022-06-30

申请号：US17383056

申请日：2021-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyeon CHO ,  Yongsuk KWON ,  Kyungsoo KIM ,  Jonghoon KIM ,  Jonghyun SEOK ,  Jonggeon LEE

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/10 ,  G11C5/06

Abstract: A memory module includes a memory substrate including a main connector and an auxiliary connector, configured to be connected to an external device; and a plurality of memory chips mounted on at least one of a first surface or a second surface of the memory substrate, wherein the main connector is disposed on one side of the memory substrate, and the auxiliary connector is disposed on the second surface of the memory substrate.

公开(公告)号：US20210349730A1

公开(公告)日：2021-11-11

申请号：US17115924

申请日：2020-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonggeon LEE ,  Kyungsoo KIM ,  Jinin SO ,  Yongsuk KWON ,  Jin JUNG ,  Jeonghyeon CHO

IPC: G06F9/4401 ,  G06N20/00

Abstract: A booting method of a computing system, which includes a memory module including a processing device connected to a plurality of memory devices, including: powering up the computing system; after powering up the computing system, performing first memory training on the plurality of memory devices by the processing device in the memory module, and generating a module ready signal indicating completion of the first memory training; after powering up the computing system, performing a first booting sequence by a host device, the host device executing basic input/output system (BIOS) code of a BIOS memory included in the computing system; waiting for the module ready signal to be received from the memory module in the host device after performing the first booting sequence; and receiving the module ready signal in the host device, and performing a second booting sequence based on the module ready signal.

公开(公告)号：US20210065836A1

公开(公告)日：2021-03-04

申请号：US16862964

申请日：2020-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngman AHN ,  Sangyeol LEE ,  Jonggeon LEE

IPC: G11C29/44 ,  G11C29/46 ,  G11C29/12 ,  G11C29/50

Abstract: A method and a memory device for testing and repairing memory cells during a power-up sequence are provided. The memory device includes a built-in self test (BIST) unit for testing a memory cell array during the power-up sequence. The BIST unit performs a test on the memory cell array in response to a power stabilization signal, or performs a test on the memory cell array in response to an impedance control (ZQ) calibration command. The BIST unit terminates a test being performed in response to a write leveling command, or terminates a test being performed in response to an active command.