公开(公告)号：US11538506B2

公开(公告)日：2022-12-27

申请号：US17356080

申请日：2021-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjin Kim ,  Yongjun Kim ,  Yonghun Kim ,  Minsu Ahn ,  Reum Oh ,  Jinyong Choi

IPC: G11C5/06 ,  G11C5/02 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor device includes a cell area in which a plurality of memory cells are arranged in an array structure, and a peripheral area in which circuits configured to drive the memory cells are arranged, the peripheral area being next to the cell area. The cell area is divided into a plurality of banks, and the plurality of banks comprise first banks having a base size and second banks having a size of 1/(2*n) (wherein n is an integer greater than or equal to 1) of the base size. The plurality of banks are arranged in a first direction and a second direction perpendicular to the first direction, and the semiconductor device has a shape of a rectangular chip which is elongated in the second direction.

公开(公告)号：US20220130841A1

公开(公告)日：2022-04-28

申请号：US17496498

申请日：2021-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaesan Kim ,  Seunghan Woo ,  Haesuk Lee ,  Youngcheon Kwon ,  Reum Oh

IPC: H01L27/108 ,  H01L23/48 ,  H01L23/528 ,  H01L29/8605 ,  H01L29/94

Abstract: A semiconductor device includes a semiconductor structure including a semiconductor substrate having an active zone with a channel; a through silicon via (TSV) structure including a power TSV configured to transmit power and a signal TSV configured to transmit a signal; and a keep-out zone located a predetermined distance away from the TSV structure and bounded by the active zone. The TSV structure penetrates the semiconductor substrate. The keep-out zone includes a first element area a first distance away from the power TSV, and a second element area a second distance away from the signal TSV.

公开(公告)号：US10592467B2

公开(公告)日：2020-03-17

申请号：US15493292

申请日：2017-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je Min Ryu ,  Reum Oh ,  Hak-Soo Yu

IPC: G06F3/06 ,  G06F15/78

Abstract: An operation method of a semiconductor memory device including a memory cell array and an internal processor configured to perform an internal processing operation includes receiving at the memory device a first mode indicator that indicates whether the memory device should operate in a processor mode or in a normal mode, receiving at the memory device processing information for the memory device, when the first mode indicator indicates that the memory device should operate in the processor mode, storing the processing information in a first memory cell region of the memory cell array, using the stored processing information to perform internal processing by the internal processor, and storing a result of the internal processing in the memory cell array.

公开(公告)号：US10241150B2

公开(公告)日：2019-03-26

申请号：US15207526

申请日：2016-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-han Woo ,  Reum Oh ,  Hae-suk Lee

IPC: G01R31/28 ,  H01L21/66 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor apparatus includes two or more semiconductor chips and a tester. The two or more semiconductor chips are electrically connected through one or more through-silicon vias (TSVs). The tester is on at least one of the two or more semiconductor chips and tests the state of at least one TSV based on an output signal of the TSV. The TSV is selected as a signal transmission TSV based on the state of the TSV.

公开(公告)号：US12203980B2

公开(公告)日：2025-01-21

申请号：US18471624

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahn Choi ,  Reum Oh

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3185

Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

公开(公告)号：US11867751B2

公开(公告)日：2024-01-09

申请号：US17872440

申请日：2022-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahn Choi ,  Reum Oh

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/2884 ,  G01R31/31715 ,  G01R31/318511

Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

公开(公告)号：US20220028431A1

公开(公告)日：2022-01-27

申请号：US17356080

申请日：2021-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjin Kim ,  Yongjun Kim ,  Yonghun Kim ,  Minsu Ahn ,  Reum Oh ,  Jinyong Choi

IPC: G11C5/06 ,  G11C5/02 ,  H01L25/065 ,  H01L23/538

Abstract: A semiconductor device includes a cell area in which a plurality of memory cells are arranged in an array structure, and a peripheral area in which circuits configured to drive the memory cells are arranged, the peripheral area being next to the cell area. The cell area is divided into a plurality of banks, and the plurality of banks comprise first banks having a base size and second banks having a size of 1/(2*n) (wherein n is an integer greater than or equal to 1) of the base size. The plurality of banks are arranged in a first direction and a second direction perpendicular to the first direction, and the semiconductor device has a shape of a rectangular chip which is elongated in the second direction.

公开(公告)号：US10916525B2

公开(公告)日：2021-02-09

申请号：US16125975

申请日：2018-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： SeungHan Woo ,  Je Min Ryu ,  Reum Oh ,  Moonhee Oh ,  BumSuk Lee

IPC: H01L25/065 ,  H01L23/48 ,  H01L25/18 ,  H01L23/00 ,  G01R31/28

Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.

公开(公告)号：US20190279963A1

公开(公告)日：2019-09-12

申请号：US16125975

申请日：2018-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： SeungHan WOO ,  Je Min Ryu ,  Reum Oh ,  Moonhee Oh ,  BumSuk Lee

IPC: H01L25/065 ,  H01L23/48 ,  H01L25/18 ,  H01L23/00 ,  G01R31/28

Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.

公开(公告)号：US10083722B2

公开(公告)日：2018-09-25

申请号：US15607699

申请日：2017-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Reum Oh ,  Je-Min Ryu ,  Pavan Kumar Kasibhatla

IPC: G11C5/06 ,  G11C5/02 ,  G06F12/084 ,  G06F12/0893 ,  G11C7/10 ,  G11C29/12 ,  G11C29/48 ,  H01L25/18

CPC classification number: G11C5/02 ,  G06F12/084 ,  G06F12/0893 ,  G11C5/025 ,  G11C7/1006 ,  G11C29/1201 ,  G11C29/48 ,  G11C2207/2245 ,  H01L25/18

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.