公开(公告)号：US20200135247A1

公开(公告)日：2020-04-30

申请号：US16721131

申请日：2019-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HOON SON ,  SI-HONG KIM ,  CHANG-KYO LEE ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA

IPC: G11C7/24 ,  G11C7/10 ,  H03H7/38

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

公开(公告)号：US20200243123A1

公开(公告)日：2020-07-30

申请号：US16848364

申请日：2020-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HOON SON ,  SI-HONG KIM ,  CHANG-KYO LEE ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA

IPC: G11C7/24 ,  H03H7/38 ,  G11C7/10

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on;enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

公开(公告)号：US20130208546A1

公开(公告)日：2013-08-15

申请号：US13743412

申请日：2013-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SI-HONG KIM ,  SEUNG-JUN BAE ,  HYE-RAN KIM ,  HO-SEOK SEOL

IPC: G11C8/18 ,  G11C7/10

CPC classification number: G11C8/18 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/41 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2272

Abstract: A latency control circuit is configured to delay a read information signal in response to a CAS latency signal and an internal clock signal to generate a delayed read information signal, and is further configured to generate a latency control signal based on the delayed read information signal in response to a plurality of sampling control signals and a plurality of transfer control signals.

Abstract translation: 延迟控制电路被配置为响应于CAS等待时间信号和内部时钟信号而延迟读取信息信号，以产生延迟的读取信息信号，并且还被配置为基于延迟读取信息信号生成等待时间控制信号 响应于多个采样控制信号和多个传送控制信号。

公开(公告)号：US20210233575A1

公开(公告)日：2021-07-29

申请号：US17141357

申请日：2021-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HOON SON ,  SI-HONG KIM ,  CHANG-KYO LEE ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA

IPC: G11C7/24 ,  H03H7/38 ,  G11C7/10

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

公开(公告)号：US20180342274A1

公开(公告)日：2018-11-29

申请号：US15918526

申请日：2018-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HOON SON ,  SI-HONG KIM ,  CHANG-KYO LEE ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA

IPC: G11C7/24 ,  G11C7/10 ,  H03H7/38

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.