公开(公告)号：US20210391000A1

公开(公告)日：2021-12-16

申请号：US17147557

申请日：2021-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOO-WOONG LEE ,  DOO-HO CHO ,  SANG SOO PARK ,  YONGKYU LEE

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4093 ,  G11C11/4076 ,  G11C11/4074

Abstract: Disclosed is a nonvolatile memory device, which includes a memory cell array that includes a plurality of memory cells, a page buffer circuit that is connected with the memory cell array through a plurality of bit lines and performs a sensing operation of sensing memory cells selected from the plurality of memory cells through the plurality of bit lines during a sensing time, an input/output circuit that performs a data output operation of outputting data from the page buffer circuit to an external device through data lines, and a sensing time control circuit that adjusts the sensing time when the data output operation is performed during the sensing time.

公开(公告)号：US20200258577A1

公开(公告)日：2020-08-13

申请号：US16752924

申请日：2020-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOO-WOONG LEE ,  HYUN-JIN KIM ,  JAE-YONG JEONG

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/32

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory cells, a page buffer circuit, and a control logic circuit. The page buffer circuit includes a plurality of first page buffers and a plurality of second page buffers, each including a sense latch, a data latch, and a cache latch. The sense latch senses data stored in the memory cell array and dumps the sensed data to the data latch, the data latch dumps the data dumped by the sense latch to the cache latch, and the cache latch transmits the data dumped by the data latch to a data I/O circuit. While the cache latch included in at least one of the plurality of first page buffers is performing a data transmit operation, the data latch included in at least one of the plurality of second page buffers performs a data dumping operation.

公开(公告)号：US20190213164A1

公开(公告)日：2019-07-11

申请号：US16056691

申请日：2018-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIWOONG KWON ,  SOO-WOONG LEE

IPC: G06F13/42 ,  G06F1/12

Abstract: A mobile device includes a slave device that receives first data provided to a serial data line in synchronization with a clock signal provided through a serial clock line, and outputs second data to the serial data line in synchronization with the clock signal; and a master device that generates the clock signal and provides the first data to the serial data line in synchronization with the generated clock signal, or receives the second data output to the serial data line in synchronization with the clock signal. The master device generates the clock signal of a first frequency upon transmitting the first data, and generates the clock signal of a second frequency, which is lower than the first frequency, upon receiving the second data.