公开(公告)号：US11348938B2

公开(公告)日：2022-05-31

申请号：US16446028

申请日：2019-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-Woo Kim ,  Sang-Gi An ,  Hyun-Gon Pyo ,  Ik-Soo Kim ,  Hee-Sook Park ,  Ji-Woon Im

IPC: H01L21/336 ,  H01L27/11582 ,  H01L21/311 ,  H01L27/11565

Abstract: In a method of manufacturing a vertical memory device, a first sacrificial layer including a nitride is formed on a substrate. A mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer is formed. The insulation layer and the second sacrificial layer include a first oxide and a second oxide, respectively. A channel is formed through the mold and the first sacrificial layer. An opening is formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer is removed through the opening to form a first gap. A channel connecting pattern is formed to fill the first gap. The second sacrificial layer is replaced with a gate electrode.