公开(公告)号：US11348938B2

公开(公告)日：2022-05-31

申请号：US16446028

申请日：2019-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-Woo Kim ,  Sang-Gi An ,  Hyun-Gon Pyo ,  Ik-Soo Kim ,  Hee-Sook Park ,  Ji-Woon Im

IPC: H01L21/336 ,  H01L27/11582 ,  H01L21/311 ,  H01L27/11565

Abstract: In a method of manufacturing a vertical memory device, a first sacrificial layer including a nitride is formed on a substrate. A mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer is formed. The insulation layer and the second sacrificial layer include a first oxide and a second oxide, respectively. A channel is formed through the mold and the first sacrificial layer. An opening is formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer is removed through the opening to form a first gap. A channel connecting pattern is formed to fill the first gap. The second sacrificial layer is replaced with a gate electrode.

公开(公告)号：US09502332B2

公开(公告)日：2016-11-22

申请号：US13927914

申请日：2013-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Heun Lim ,  Hyo-Jung Kim ,  Ji-Woon Im ,  Kyung-Hyun Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/115

CPC classification number: H01L23/48 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes, a first recess formed in the electrode structure on the connection region and disposed between the cell array region and a second recess formed in the electrode structure on the connection region, and a plurality of vertical wirings formed on the plurality of electrodes exposed by the first recess.

Abstract translation: 一种非易失性存储器件，包括：包括单元阵列区域和连接区域的基板;形成在单元阵列区域上的电极结构和连接区域，并且包括多个层压电极;形成在电极结构中的第一凹部， 并且布置在单元阵列区域和形成在连接区域上的电极结构中的第二凹槽之间，以及形成在由第一凹部暴露的多个电极上的多个垂直布线。