公开(公告)号：US11348938B2

公开(公告)日：2022-05-31

申请号：US16446028

申请日：2019-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-Woo Kim ,  Sang-Gi An ,  Hyun-Gon Pyo ,  Ik-Soo Kim ,  Hee-Sook Park ,  Ji-Woon Im

IPC: H01L21/336 ,  H01L27/11582 ,  H01L21/311 ,  H01L27/11565

Abstract: In a method of manufacturing a vertical memory device, a first sacrificial layer including a nitride is formed on a substrate. A mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer is formed. The insulation layer and the second sacrificial layer include a first oxide and a second oxide, respectively. A channel is formed through the mold and the first sacrificial layer. An opening is formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer is removed through the opening to form a first gap. A channel connecting pattern is formed to fill the first gap. The second sacrificial layer is replaced with a gate electrode.

公开(公告)号：US09524879B2

公开(公告)日：2016-12-20

申请号：US14669221

申请日：2015-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Su Lee ,  Young-Wook Park ,  Hee-Sook Park ,  Dong-Bok Lee ,  Jong-Myeong Lee

IPC: H01L21/336 ,  H01L21/311 ,  H01L21/768 ,  H01L21/288 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/31111 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/76895 ,  H01L27/10855 ,  H01L29/4236 ,  H01L29/78

Abstract: Semiconductor devices, and methods for fabricating a semiconductor device, include forming a contact hole penetrating an interlayer insulating layer and exposing a conductor defining a bottom surface of the contact hole, forming a sacrificial layer filling the contact hole, forming a first trench overlapping a part of the contact hole by removing at least a part of the sacrificial layer, forming a spacer filling the first trench, forming a second trench by removing a remainder of the sacrificial layer, and forming a metal electrode filling the contact hole and the second trench using electroless plating.

Abstract translation: 半导体器件以及半导体器件的制造方法包括：形成贯穿层间绝缘层的接触孔，露出限定接触孔的底面的导体，形成填充接触孔的牺牲层，形成与第一沟槽重叠的部分 通过去除所述牺牲层的至少一部分，形成填充所述第一沟槽的间隔物，通过去除所述牺牲层的剩余部分形成第二沟槽，以及使用以下方式形成填充所述接触孔和所述第二沟槽的金属电极： 无电镀。

公开(公告)号：US09178039B2

公开(公告)日：2015-11-03

申请号：US14052072

申请日：2013-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hwa Park ,  Woong-Hee Sohn ,  Man-Sug Kang ,  Hee-Sook Park

IPC: H01L29/66 ,  H01L27/108

CPC classification number: H01L29/66621 ,  H01L27/10876

Abstract: A semiconductor device includes a gate trench across an active region of a semiconductor substrate, a gate structure filling the gate trench, and source/drain regions formed in the active region at respective sides of the gate structure. The gate structure includes a sequentially stacked gate electrode and insulating capping pattern, and a gate dielectric layer between the gate electrode and the active region. The gate electrode is located at a lower level than an upper surface of the active region and includes a barrier conductive pattern and a gate conductive pattern. The gate conductive pattern includes a first part having a first width and a second part having a second width greater than the first width. The barrier conductive pattern is interposed between the first part of the gate conductive pattern and the gate dielectric layer.

Abstract translation: 半导体器件包括跨越半导体衬底的有源区的栅极沟槽，填充栅极沟槽的栅极结构以及形成在栅极结构的相应侧的有源区中的源极/漏极区。 栅极结构包括顺序层叠的栅极电极和绝缘覆盖图案，以及栅电极和有源区之间的栅介质层。 栅电极位于比有源区的上表面更低的电平，并且包括阻挡导电图案和栅极导电图案。 栅极导电图案包括具有第一宽度的第一部分和具有大于第一宽度的第二宽度的第二部分。 阻挡导电图案插入在栅极导电图案的第一部分和栅极电介质层之间。