公开(公告)号：US09715344B2

公开(公告)日：2017-07-25

申请号：US14620305

申请日：2015-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Kwon Moon ,  Seung-Uk Shin ,  Kyung-Ho Kim

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0616 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/7205

Abstract: A flash memory system is provided. The flash memory system includes a memory device including a memory cell array including at least one data block and a controller that determines whether to end background garbage collection according to a lifespan index of the at least one data block. The lifespan index may be decreased by the background garbage collection. The controller may end the background garbage collection when the decreased lifespan index is equal to or higher than a reference value.

公开(公告)号：US11487576B2

公开(公告)日：2022-11-01

申请号：US17318554

申请日：2021-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sng-Hoon Park ,  In-Soo Kim ,  Jong-Won Kim ,  Sang-Kwon Moon

IPC: G06F12/00 ,  G06F9/48 ,  G06F3/06

Abstract: A memory controller is disclosed. The memory controller is configured to control the execution of a suspend operation by a memory device. The memory controller includes: a processor configured to output an operation control signal when the memory device is performing a program/erase operation; and a suspend operation manager configured to output suspend mode change information based on the operation control signal and suspend information, wherein the processor is further configured to control the memory controller such that the memory controller outputs a suspend mode change command and a suspend command based on the suspend mode change information.

公开(公告)号：US11037628B2

公开(公告)日：2021-06-15

申请号：US16543532

申请日：2019-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shin-Ho Oh ,  Min-Cheol Kwon ,  Sang-Kwon Moon ,  Sang-Won Jung

IPC: G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/08 ,  G06F3/06

Abstract: A nonvolatile memory device includes multi-level cells in a memory cell array including a plurality of memory blocks, and each of the memory blocks includes a plurality of pages. A method of operating the nonvolatile memory device includes pre-programming multi-bit data in a pre-program block of the memory blocks, dividing the multi-level cells into a plurality of state groups based on state codes indicating states of the multi-level cells to generate digest data indicating state group codes corresponding to the state groups, and programming the digest data in a digest block of the memory blocks.

公开(公告)号：US11610631B2

公开(公告)日：2023-03-21

申请号：US17316463

申请日：2021-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shin-Ho Oh ,  Min-Cheol Kwon ,  Sang-Kwon Moon ,  Sang-Won Jung

IPC: G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/08 ,  G06F3/06

Abstract: A nonvolatile memory device includes multi-level cells in a memory cell array including a plurality of memory blocks, and each of the memory blocks includes a plurality of pages. A method of operating the nonvolatile memory device includes pre-programming multi-bit data in a pre-program block of the memory blocks, dividing the multi-level cells into a plurality of state groups based on state codes indicating states of the multi-level cells to generate digest data indicating state group codes corresponding to the state groups, and programming the digest data in a digest block of the memory blocks.

公开(公告)号：US11036544B2

公开(公告)日：2021-06-15

申请号：US16717720

申请日：2019-12-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sng-Hoon Park ,  In-Soo Kim ,  Jong-Won Kim ,  Sang-Kwon Moon

IPC: G06F12/00 ,  G06F9/48 ,  G06F3/06

Abstract: A memory controller is disclosed. The memory controller is configured to control the execution of a suspend operation by a memory device. The memory controller includes: a processor configured to output an operation control signal when the memory device is performing a program/erase operation; and a suspend operation manager configured to output suspend mode change information based on the operation control signal and suspend information, wherein the processor is further configured to control the memory controller such that the memory controller outputs a suspend mode change command and a suspend command based on the suspend mode change information.