公开(公告)号：US11646305B2

公开(公告)日：2023-05-09

申请号：US16946620

申请日：2020-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungok Lee ,  Sangdo Park ,  Jun Seomun ,  Bonghyun Lee

IPC: H01L27/00 ,  H01L27/02

CPC classification number: H01L27/0207

Abstract: Semiconductor devices may include standard cells arranged in a first direction and a second direction intersecting the first direction. Both the first and second directions may be parallel to an upper surface of the substrate. Each of the standard cells may include semiconductor elements. The semiconductor device may also include filler cells between two standard cells, and each of the filler cells may include a filler active region and a filler contact connected to the filler active region and may extend in the first direction. The semiconductor device may further include a lower wiring pattern electrically connected to at least one of the semiconductor elements and may extend into at least one of the filler cells in the second direction, and the filler contacts may include wiring filler contacts lower than the lower wiring pattern and connected to at least one of the lower wiring pattern.

公开(公告)号：US20210384186A1

公开(公告)日：2021-12-09

申请号：US17106787

申请日：2020-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongcheul Kim ,  Jooyeon Kwon ,  Sangdo Park

IPC: H01L27/02 ,  H01L27/092 ,  G06F30/392

Abstract: An integrated circuit (IC) includes: a first cell including an input pin and an output pin extending in a first direction; a second cell adjacent to the first cell in the first direction and including an input pin and an output pin extending in the first direction; a first cell isolation layer extending between the first cell and the second cell in a second direction crossing the first direction; and a first wire extending in the first direction, overlapping the first cell isolation layer, and being connected to the output pin of the first cell and the input pin of the second cell, wherein the output pin of the first cell, the input pin of the second cell, and the first wire are formed in a first conductive layer as a first pattern extending in the first direction.

公开(公告)号：US11680987B2

公开(公告)日：2023-06-20

申请号：US17864729

申请日：2022-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SAMSUNG SDI CO., LTD.

Inventor： Sangdo Park ,  Young Hun Sung ,  Tae Won Song ,  Tae Kyung Lee

IPC: G01R31/367 ,  G01R31/36 ,  G01R31/396 ,  G01R31/382

CPC classification number: G01R31/367 ,  G01R31/3646 ,  G01R31/3648 ,  G01R31/382 ,  G01R31/396

Abstract: A processor-implemented battery management method includes: estimating state information of a plurality of battery cells in a battery pack using a first battery state estimation model; determining whether state information of at least one of the plurality of battery cells is to be estimated using a second battery state estimation model; and estimating the state information of the at least one battery cell using the second model, in response to a result of the determining being that the state information of the at least one battery cell is to be estimated using the second model.

公开(公告)号：US11430779B2

公开(公告)日：2022-08-30

申请号：US17028855

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewan Yang ,  Wootae Kim ,  Hyungock Kim ,  Sangdo Park ,  Jun Seomun

IPC: H01L27/02 ,  H01L21/768 ,  H01L27/088 ,  H01L23/522

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The method includes placing a standard cell, resizing a power via pattern in such a way that the power via pattern has a different width from a width of other via pattern, and applying different design rules to the power via pattern and the other via pattern, respectively, to perform a routing operation on the standard cell.

公开(公告)号：US11422191B2

公开(公告)日：2022-08-23

申请号：US16512484

申请日：2019-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SAMSUNG SDI CO., LTD.

Inventor： Sangdo Park ,  Young Hun Sung ,  Tae Won Song ,  Tae Kyung Lee

IPC: G01R31/396 ,  G01R31/367 ,  G01R31/36 ,  G01R31/382

Abstract: A processor-implemented battery management method includes: estimating state information of a plurality of battery cells in a battery pack using a first battery state estimation model; determining whether state information of at least one of the plurality of battery cells is to be estimated using a second battery state estimation model; and estimating the state information of the at least one battery cell using the second model, in response to a result of the determining being that the state information of the at least one battery cell is to be estimated using the second model.

公开(公告)号：US11923354B2

公开(公告)日：2024-03-05

申请号：US17338201

申请日：2021-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dayeon Cho ,  Hyungock Kim ,  Sangdo Park

IPC: H01L27/02 ,  G06F30/392 ,  G06F30/398 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0207 ,  G06F30/392 ,  G06F30/398 ,  H01L23/5286 ,  H01L27/0925 ,  H01L29/0657 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor device includes standard cells in a first direction parallel to an upper surface of a substrate and a second direction intersecting the first direction, and filler cells between ones of the standard cells. Each of the standard cells includes an active region, a gate structure that intersects the active region, source/drain regions on the active region on both sides of the gate structure, and interconnection lines. Each of the filler cells includes a filler active region and a filler gate structure that intersects the filler active region. The standard cells include first to third standard cells in first to third rows sequentially in the second direction, respectively. First interconnection lines are arranged with a first pitch, second interconnection lines are arranged with a second pitch, and third interconnection lines are arranged with a third pitch different from the first and second pitches.

公开(公告)号：US11630157B2

公开(公告)日：2023-04-18

申请号：US16281438

申请日：2019-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kaeweon You ,  Sangdo Park

IPC: G01R31/367 ,  G01R31/3828 ,  G01R31/3842 ,  G01R31/388 ,  B60L53/10 ,  B60L58/12 ,  G01R31/36 ,  G06N3/08

Abstract: A processor-implemented method of estimating a state of a battery includes acquiring current information and voltage information of a battery; determining time interval values based on the acquired current information such that current integration values corresponding to the time variation values satisfy a condition; determining voltage values corresponding to the determined time interval values in the acquired voltage information; and determining state information of the battery based on the determined voltage values.

公开(公告)号：US11557584B2

公开(公告)日：2023-01-17

申请号：US17106787

申请日：2020-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongcheul Kim ,  Jooyeon Kwon ,  Sangdo Park

IPC: H01L27/02 ,  G06F30/392 ,  H01L27/092 ,  H01L23/528

Abstract: An integrated circuit (IC) includes: a first cell including an input pin and an output pin extending in a first direction; a second cell adjacent to the first cell in the first direction and including an input pin and an output pin extending in the first direction; a first cell isolation layer extending between the first cell and the second cell in a second direction crossing the first direction; and a first wire extending in the first direction, overlapping the first cell isolation layer, and being connected to the output pin of the first cell and the input pin of the second cell, wherein the output pin of the first cell, the input pin of the second cell, and the first wire are formed in a first conductive layer as a first pattern extending in the first direction.

公开(公告)号：US11410988B2

公开(公告)日：2022-08-09

申请号：US17181672

申请日：2021-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： SungOk Lee ,  Sangdo Park ,  Dayeon Cho

IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/092

Abstract: An integrated circuit includes a standard cell continuously arranged on a first row and on a second row, the first row and second row extending parallel with each other in a first direction, the first row and the second row adjacent to each other in a second direction crossing the first direction, a first cell separator contacting a first row boundary of the standard cell on the first row and extending in the second direction, and a second cell separator contacting a second row boundary of the standard cell on the second row and extending in the second direction. The first cell separator and the second cell separator are discontinuous on a first row to second row boundary of the first row and the second row.