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公开(公告)号：US11995391B2
公开(公告)日：2024-05-28
申请号：US17702879
申请日：2022-03-24
发明人： Yongdeok Kim , Munjun Seo , Bonghyun Lee
IPC分类号： G06F30/392 , G03F1/36 , G06F30/3953 , G06F30/398
CPC分类号： G06F30/3953 , G03F1/36 , G06F30/392 , G06F30/398
摘要： Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an area-oriented region and a performance-oriented region, standard cells disposed on each of the area-oriented region and the performance-oriented region, and a routing metal layer on the standard cells. The routing metal layer includes first routing lines on the area-oriented region and second routing lines on the performance-oriented region. The smallest line width of the first routing lines is a first width, the smallest line width of the second routing lines is a second width greater than the first width, a pitch between the first routing lines is a first pitch, and a pitch between the second routing lines is a second pitch greater than the first pitch.
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2.发明授权公开(公告)号：US11776950B2
公开(公告)日：2023-10-03
申请号：US17951381
申请日：2022-09-23
发明人： Bonghyun Lee
IPC分类号： H01L27/02 , G06F30/392 , H01L23/528 , H01L27/092
CPC分类号： H01L27/0207 , G06F30/392 , H01L23/5286 , H01L27/0924
摘要： An IC includes: a plurality of first cells placed in a series of first rows extending in a first horizontal direction and each having a first height; and a plurality of second cells placed in a series of second rows extending in the first horizontal direction and each having a second height different from the first height, wherein a total height of the series of first rows corresponds to a multiple of a height of a first multi-height cell with a maximum height among the plurality of first cells, and a total height of the series of second rows corresponds to a multiple of a height of a second multi-height cell with a maximum height among the plurality of second cells.
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3.发明授权公开(公告)号：US11495592B2
公开(公告)日：2022-11-08
申请号：US17136754
申请日：2020-12-29
发明人： Bonghyun Lee
IPC分类号： H01L27/02 , G06F30/392 , H01L23/528 , H01L27/092
摘要： An IC includes: a plurality of first cells placed in a series of first rows extending in a first horizontal direction and each having a first height; and a plurality of second cells placed in a series of second rows extending in the first horizontal direction and each having a second height different from the first height, wherein a total height of the series of first rows corresponds to a multiple of a height of a first multi-height cell with a maximum height among the plurality of first cells, and a total height of the series of second rows corresponds to a multiple of a height of a second multi-height cell with a maximum height among the plurality of second cells.
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公开(公告)号：US11646305B2
公开(公告)日：2023-05-09
申请号：US16946620
申请日：2020-06-30
发明人： Sungok Lee , Sangdo Park , Jun Seomun , Bonghyun Lee
CPC分类号： H01L27/0207
摘要： Semiconductor devices may include standard cells arranged in a first direction and a second direction intersecting the first direction. Both the first and second directions may be parallel to an upper surface of the substrate. Each of the standard cells may include semiconductor elements. The semiconductor device may also include filler cells between two standard cells, and each of the filler cells may include a filler active region and a filler contact connected to the filler active region and may extend in the first direction. The semiconductor device may further include a lower wiring pattern electrically connected to at least one of the semiconductor elements and may extend into at least one of the filler cells in the second direction, and the filler contacts may include wiring filler contacts lower than the lower wiring pattern and connected to at least one of the lower wiring pattern.
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5.发明申请公开(公告)号：US20220129612A1
公开(公告)日：2022-04-28
申请号：US17238874
申请日：2021-04-23
发明人： Bonghyun Lee
IPC分类号： G06F30/396 , H01L23/528
摘要： A method of routing a clock tree including a plurality of clock nets of an integrated circuit, where each of the plurality of clock nets includes at least one clock repeater, includes determining a level of a clock net of the plurality of clock nets based on a number of clock gating cells that a clock signal passes through until the clock net receives the clock signal from a clock source and routing a plurality of conductive lines in each of the plurality of clock nets by applying different routing rules to clock nets having different levels based on the determined level. Each of the plurality of clock nets is configured to transfer the clock signal to a plurality of synchronous elements or another clock net. The plurality of synchronous elements operate in synchronization with the clock signal and are included in the integrated circuit.
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公开(公告)号：US11314919B2
公开(公告)日：2022-04-26
申请号：US17022233
申请日：2020-09-16
发明人： Yongdeok Kim , Munjun Seo , Bonghyun Lee
IPC分类号： G06F30/30 , G06F30/3953 , G03F1/36 , G06F30/398 , G06F30/392
摘要： Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an area-oriented region and a performance-oriented region, standard cells disposed on each of the area-oriented region and the performance-oriented region, and a routing metal layer on the standard cells. The routing metal layer includes first routing lines on the area-oriented region and second routing lines on the performance-oriented region. The smallest line width of the first routing lines is a first width, the smallest line width of the second routing lines is a second width greater than the first width, a pitch between the first routing lines is a first pitch, and a pitch between the second routing lines is a second pitch greater than the first pitch.
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公开(公告)号：US11727184B2
公开(公告)日：2023-08-15
申请号：US17877483
申请日：2022-07-29
发明人： Bonghyun Lee , Jungho Do
IPC分类号： G06F30/00 , G06F30/392 , H01L23/528 , H01L27/02
CPC分类号： G06F30/392 , H01L23/5286 , H01L27/0207
摘要： An integrated circuit includes a first column including a plurality of first cells aligned and placed in a plurality of first rows, each first row having a first width and extending in a first horizontal direction, a second column including a plurality of second cells aligned and placed in a plurality of second rows, each second row having a second width and extending in the first horizontal direction, and an interface column extending in a second horizontal direction perpendicular to the first horizontal direction between the first column and the second column, wherein the interface column includes at least one well tap configured to provide a first supply voltage to a well, and at least one substrate tap configured to provide a second supply voltage to a substrate.
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公开(公告)号：US11494544B2
公开(公告)日：2022-11-08
申请号：US17183630
申请日：2021-02-24
发明人： Bonghyun Lee , Jungho Do
IPC分类号： G06F30/00 , G06F30/392 , H01L27/02 , H01L23/528
摘要： An integrated circuit includes a first column including a plurality of first cells aligned and placed in a plurality of first rows, each first row having a first width and extending in a first horizontal direction, a second column including a plurality of second cells aligned and placed in a plurality of second rows, each second row having a second width and extending in the first horizontal direction, and an interface column extending in a second horizontal direction perpendicular to the first horizontal direction between the first column and the second column, wherein the interface column includes at least one well tap configured to provide a first supply voltage to a well, and at least one substrate tap configured to provide a second supply voltage to a substrate.
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9.发明授权Integrated circuit having main route and detour route for signal transmission and integrated circuit package including the same 有权具有用于信号传输的主要路线和绕行路线的集成电路和包括其的集成电路封装公开(公告)号：US09524922B2
公开(公告)日：2016-12-20
申请号：US14665428
申请日：2015-03-23
发明人： Kyounghwan Lim , Hyoun Soo Park , Kee Sup Kim , Bonghyun Lee , Chul Rim , JungYun Choi , Taewhan Kim , Heechun Park
IPC分类号： H01L23/48 , H03K19/00 , H01L21/66 , H01L23/522
CPC分类号： H01L23/481 , H01L22/14 , H01L22/22 , H01L23/5226 , H01L25/0657 , H01L2924/0002 , H03K19/00 , H01L2924/00
摘要： The integrated circuit includes first and second vias, a first buffer configured to receive a signal transmitted from the first via, a second buffer configured to receive a signal transmitted from the second via, a first detour circuit configured to receive a signal transmitted through the second buffer, a second detour circuit configured to receive a signal transmitted through the first buffer, a first selector configured to selectively output one of the signal transmitted from the first via and a signal transmitted through the first detour circuit, and a second selector configured to selectively output one of the signal transmitted from the second via and a signal transmitted through the second detour circuit. Each of the first and second buffers and the first and second detour circuits transmits a signal in only one direction.
摘要翻译： 集成电路包括第一和第二通孔，第一缓冲器被配置为接收从第一通路发送的信号，第二缓冲器，被配置为接收从第二通路发送的信号，第一迂回电路被配置为接收通过第二通孔传输的信号 缓冲器，被配置为接收通过第一缓冲器传输的信号的第二迂回电路，第一选择器，被配置为选择性地输出从第一通孔传输的信号和通过第一迂回电路传输的信号之一;以及第二选择器，其被配置为选择性地 输出从第二通路发送的信号中的一个信号和通过第二迂回电路发送的信号。 第一和第二缓冲器以及第一和第二绕路电路中的每一个仅在一个方向上传输信号。
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10.发明授权公开(公告)号：US12056430B2
公开(公告)日：2024-08-06
申请号：US17238874
申请日：2021-04-23
发明人： Bonghyun Lee
IPC分类号： G06F30/396 , H01L23/528 , G06F117/04
CPC分类号： G06F30/396 , H01L23/5286 , G06F2117/04
摘要： A method of routing a clock tree including a plurality of clock nets of an integrated circuit, where each of the plurality of clock nets includes at least one clock repeater, includes determining a level of a clock net of the plurality of clock nets based on a number of clock gating cells that a clock signal passes through until the clock net receives the clock signal from a clock source and routing a plurality of conductive lines in each of the plurality of clock nets by applying different routing rules to clock nets having different levels based on the determined level. Each of the plurality of clock nets is configured to transfer the clock signal to a plurality of synchronous elements or another clock net. The plurality of synchronous elements operate in synchronization with the clock signal and are included in the integrated circuit.
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