Memory device performing parallel calculation processing, operating method thereof, and operating method of memory controller controlling the memory device

    公开(公告)号:US11416178B2

    公开(公告)日:2022-08-16

    申请号:US17014667

    申请日:2020-09-08

    Abstract: A memory device includes a memory bank including a plurality of banks, each including a memory cell array; a calculation logic including a plurality of processor-in-memory (PIM) circuits arranged in correspondence to the banks, each of the plurality of PIM circuits performing calculation processing using at least one selected from data provided from a host and information read from a corresponding bank among the banks; and a control logic configured to control a memory operation on the memory bank in response to a command and/or an address, each received from the host, or to control the calculation logic to perform the calculation processing, wherein reading operations are respectively performed in parallel on the banks for the calculation processing, offsets having different values are respectively configured for the banks, and information is read from different positions in respective memory cell arrays of the banks and provided to the PIM circuits.

    Memory modules and stacked memory devices

    公开(公告)号:US11295805B2

    公开(公告)日:2022-04-05

    申请号:US17095008

    申请日:2020-11-11

    Abstract: A memory module includes semiconductor memory devices mounted on a circuit board and a control device mounted on the circuit board. Each semiconductor memory device includes a memory cell array to store data. The control device receives a command and an access address from an external device and provides the command and the access address to the semiconductor memory devices. Each semiconductor memory device performs an address swapping operation to randomly swap a portion of bits of the access address to generate a swapped address in response to a power-up signal or a reset signal, and enables a respective target word-line from among word-lines in the memory cell array such that two or more of the semiconductor memory devices enable different target word-lines in response to the access address.

    MEMORY MODULES AND STACKED MEMORY DEVICES

    公开(公告)号:US20210327489A1

    公开(公告)日:2021-10-21

    申请号:US17095008

    申请日:2020-11-11

    Abstract: A memory module includes semiconductor memory devices mounted on a circuit board and a control device mounted on the circuit board. Each semiconductor memory device includes a memory cell array to store data. The control device receives a command and an access address from an external device and provides the command and the access address to the semiconductor memory devices. Each semiconductor memory device performs an address swapping operation to randomly swap a portion of bits of the access address to generate a swapped address in response to a power-up signal or a reset signal, and enables a respective target word-line from among word-lines in the memory cell array such that two or more of the semiconductor memory devices enable different target word-lines in response to the access address.

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