公开(公告)号：US12001699B2

公开(公告)日：2024-06-04

申请号：US18145186

申请日：2022-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngcheon Kwon ,  Jaesan Kim ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  H01L25/18

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1069 ,  G11C7/222 ,  H01L25/18

Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.

公开(公告)号：US11335392B2

公开(公告)日：2022-05-17

申请号：US16903055

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngcheon Kwon ,  Sanghyuk Kwon ,  Kyomin Sohn ,  Jaeyoun Youn ,  Haesuk Lee

IPC: G11C11/406 ,  G11C11/408

Abstract: A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.

公开(公告)号：US20220139433A1

公开(公告)日：2022-05-05

申请号：US17574174

申请日：2022-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngcheon Kwon ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee ,  Jihyun Choi

IPC: G11C7/22 ,  G11C7/10

Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

公开(公告)号：US10607965B2

公开(公告)日：2020-03-31

申请号：US16044886

申请日：2018-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haesuk Lee ,  So-Young Kim ,  Seung-Han Woo

IPC: H01L25/065 ,  H01L23/538 ,  G11C5/02 ,  G11C5/06

Abstract: A stacked semiconductor device includes a plurality of semiconductor dies stacked in a first direction, M data paths electrically connecting the plurality of semiconductor dies, one data path including one or more through-silicon vias, where M is a positive integer, a transmission circuit including M serialization units configured to serialize P transmission signals to M serial signals and output the M serial signals to the M data paths, respectively, where P is a positive integer greater than M and a reception circuit including M parallelization units configured to receive the M serial signals from the M data paths and parallelize the M serial signals to P reception signals corresponding to the P transmission signals. The number of the through-silicon vias is reduced by serializing the transmission signals, transferring the serialized signals through the smaller number of data paths between the stacked semiconductor dies and then parallelizing the transferred signals.

公开(公告)号：US12250807B2

公开(公告)日：2025-03-11

申请号：US17496498

申请日：2021-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaesan Kim ,  Seunghan Woo ,  Haesuk Lee ,  Youngcheon Kwon ,  Reum Oh

IPC: H10B12/00 ,  H01L23/48 ,  H01L23/528 ,  H01L29/8605 ,  H01L29/94

Abstract: A semiconductor device includes a semiconductor structure including a semiconductor substrate having an active zone with a channel; a through silicon via (TSV) structure including a power TSV configured to transmit power and a signal TSV configured to transmit a signal; and a keep-out zone located a predetermined distance away from the TSV structure and bounded by the active zone. The TSV structure penetrates the semiconductor substrate. The keep-out zone includes a first element area a first distance away from the power TSV, and a second element area a second distance away from the signal TSV.

公开(公告)号：US11561711B2

公开(公告)日：2023-01-24

申请号：US17335307

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngcheon Kwon ,  Jaesan Kim ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  H01L25/18

Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.

公开(公告)号：US11250894B2

公开(公告)日：2022-02-15

申请号：US17145941

申请日：2021-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngcheon Kwon ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee ,  Jihyun Choi

IPC: G11C8/00 ,  G11C7/22 ,  G11C7/10

Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

公开(公告)号：US11152053B2

公开(公告)日：2021-10-19

申请号：US16994796

申请日：2020-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Seongil O ,  Haesuk Lee

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/406 ,  G11C8/12 ,  G11C11/4076

Abstract: A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.

公开(公告)号：US12002543B2

公开(公告)日：2024-06-04

申请号：US18299440

申请日：2023-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngcheon Kwon ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee ,  Jihyun Choi

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084

Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

公开(公告)号：US11763876B2

公开(公告)日：2023-09-19

申请号：US17475479

申请日：2021-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Seongil O ,  Haesuk Lee

IPC: G11C8/12 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/4087 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/40618

Abstract: A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.