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    Memory device performing configurable mode setting and method of operating the same
    2.
    发明授权
    Memory device performing configurable mode setting and method of operating the same 有权

    公开(公告)号：US11561711B2

    公开(公告)日：2023-01-24

    申请号：US17335307

    申请日：2021-06-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngcheon Kwon ,  Jaesan Kim ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee

    IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  H01L25/18

    Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.

    Memory device for supporting new command input scheme and method of operating the same
    3.
    发明授权
    Memory device for supporting new command input scheme and method of operating the same 有权

    公开(公告)号：US11250894B2

    公开(公告)日：2022-02-15

    申请号：US17145941

    申请日：2021-01-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngcheon Kwon ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee ,  Jihyun Choi

    IPC: G11C8/00 ,  G11C7/22 ,  G11C7/10

    Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

    Memory device for supporting new command input scheme and method of operating the same
    4.
    发明授权
    Memory device for supporting new command input scheme and method of operating the same 有权

    公开(公告)号：US12002543B2

    公开(公告)日：2024-06-04

    申请号：US18299440

    申请日：2023-04-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngcheon Kwon ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee ,  Jihyun Choi

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084

    Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

    Semiconductor memory device and system including the same
    5.
    发明授权
    Semiconductor memory device and system including the same 有权

    公开(公告)号：US11599301B2

    公开(公告)日：2023-03-07

    申请号：US17245325

    申请日：2021-04-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Haesuk Lee ,  Reum Oh ,  Youngcheon Kwon ,  Beomyong Kil ,  Jemin Ryu ,  Jihyun Choi

    IPC: G06F3/06 ,  G11C7/22

    Abstract: A semiconductor memory device includes an interface semiconductor die, at least one memory semiconductor die, and through-silicon vias connecting the interface semiconductor die and the memory semiconductor die. The interface semiconductor die includes command pins to receive command signals transferred from a memory controller and an interface command decoder to decode the command signals. The memory semiconductor die includes a memory integrated circuit configured to store data and a memory command decoder to decode the command signals transferred from the interface semiconductor die. The interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller. The interface and memory command decoders generate interface and memory clock enable signals to control clock supply with respect to the interface and memory semiconductor dies based on a power mode command transferred through the plurality of command pins from the memory controller.

    High bandwidth memories and systems including the same
    6.
    发明授权
    High bandwidth memories and systems including the same 有权

    公开(公告)号：US11127713B2

    公开(公告)日：2021-09-21

    申请号：US16926189

    申请日：2020-07-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngcheon Kwon ,  Kyomin Sohn ,  Jaeyoun Youn

    IPC: H01L25/065 ,  H01L23/538 ,  H01L21/66

    Abstract: High bandwidth memories and systems including the same may include a buffer die, a plurality of memory dies stacked on the buffer die, a plurality of dummy bump groups in edge regions of the buffer die and the plurality of memory dies, and a plurality of signal line groups. Each of the plurality of dummy bump groups includes dummy bumps spaced apart from each other between each pair of adjacent dies and configured to connect the two adjacent dies to each other. Each of the signal line groups includes a plurality of signal lines configured to transmit a corresponding signal among an input signal and a plurality of bump crack detection signals applied to an input dummy bump of each of the plurality of dummy bump groups via sequential transmission through the plurality of dummy bumps to an output dummy bump during a bump crack test operation.

    MEMORY DEVICE FOR SUPPORTING NEW COMMAND INPUT SCHEME AND METHOD OF OPERATING THE SAME
    10.
    发明申请
    MEMORY DEVICE FOR SUPPORTING NEW COMMAND INPUT SCHEME AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20220139433A1

    公开(公告)日：2022-05-05

    申请号：US17574174

    申请日：2022-01-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngcheon Kwon ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee ,  Jihyun Choi

    IPC: G11C7/22 ,  G11C7/10

    Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

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