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    MEMORY DEVICE PERFORMING CONFIGURABLE MODE SETTING AND METHOD OF OPERATING THE SAME
    1.
    发明申请
    MEMORY DEVICE PERFORMING CONFIGURABLE MODE SETTING AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20230138048A1

    公开(公告)日：2023-05-04

    申请号：US18145186

    申请日：2022-12-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngcheon Kwon ,  Jaesan Kim ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee

    IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  H01L25/18

    Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.

    Memory device for supporting new command input scheme and method of operating the same
    2.
    发明授权
    Memory device for supporting new command input scheme and method of operating the same 有权

    公开(公告)号：US11636885B2

    公开(公告)日：2023-04-25

    申请号：US17574174

    申请日：2022-01-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngcheon Kwon ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee ,  Jihyun Choi

    IPC: G11C7/22 ,  G11C7/10

    Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

    Semiconductor memory devices
    4.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US11366716B2

    公开(公告)日：2022-06-21

    申请号：US17088900

    申请日：2020-11-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yesin Ryu ,  Namsung Kim ,  Sanguhn Cha ,  Jaeyoun Youn ,  Kijun Lee

    IPC: G06F11/10 ,  H01L25/065

    Abstract: A semiconductor memory device including: a buffer die; memory dies stacked on the buffer die; and TSVs, at least one of the memory dies includes: a memory cell array; an error correction code (ECC) engine; an error information register; and a control logic circuit configured to control the ECC engine to perform a read-modify-write operation, wherein the control logic circuit is configured to: record, in the error information register, a first address associated with a first codeword based on the an generation signal and a first syndrome obtained by an ECC decoding; and determine an error attribute of the first codeword based on a change of the first syndrome, recorded in the error information register, based on a plurality of read-modify-write operations.

    Semiconductor memory devices and memory systems
    5.
    发明授权
    Semiconductor memory devices and memory systems 有权

    公开(公告)号：US11170868B2

    公开(公告)日：2021-11-09

    申请号：US16864787

    申请日：2020-05-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yesin Ryu ,  Sanguhn Cha ,  Sunghye Cho ,  Kijun Lee ,  Myungkyu Lee ,  Youngcheon Kwon ,  Jaeyoun Youn

    IPC: G11C29/00 ,  G11C29/42 ,  G11C29/14 ,  G11C7/10 ,  G11C29/44 ,  G11C29/12

    Abstract: A semiconductor memory device includes a memory cell array and an interface circuit including an error correction code (ECC) engine. The memory cell array includes a plurality of volatile memory cells, a normal cell region and a parity cell region. The interface circuit, in a write operation, receives main data and first parity data from an external device, the first parity data being generated based on a first ECC and stores the main data in the normal cell region and the first parity data in the parity cell region. The interface circuit, in a read operation, performs an ECC decoding on the main data using a second ECC, based on the first parity data to correct a first type of error in the main data. The second ECC has a parity check matrix which is the same as a parity check matrix of the first ECC.

    MEMORY DEVICE FOR SUPPORTING NEW COMMAND INPUT SCHEME AND METHOD OF OPERATING THE SAME
    6.
    发明公开
    MEMORY DEVICE FOR SUPPORTING NEW COMMAND INPUT SCHEME AND METHOD OF OPERATING THE SAME 审中-公开

    公开(公告)号：US20240282353A1

    公开(公告)日：2024-08-22

    申请号：US18654443

    申请日：2024-05-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngcheon KWON ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee ,  Jihyun Choi

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084

    Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

    MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE
    9.
    发明申请
    MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE 有权

    公开(公告)号：US20220318164A1

    公开(公告)日：2022-10-06

    申请号：US17685987

    申请日：2022-03-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hyuk KWON ,  Nam Sung Kim ,  Kyomin Sohn ,  Jaeyoun Youn

    IPC: G06F13/16 ,  H01L25/065

    Abstract: A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.

    MEMORY DEVICE PERFORMING CONFIGURABLE MODE SETTING AND METHOD OF OPERATING THE SAME
    10.
    发明申请
    MEMORY DEVICE PERFORMING CONFIGURABLE MODE SETTING AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20220075541A1

    公开(公告)日：2022-03-10

    申请号：US17335307

    申请日：2021-06-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngcheon Kwon ,  Jaesan Kim ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee

    IPC: G06F3/06 ,  H01L25/18 ,  G11C7/10 ,  G11C7/22

    Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.

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