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公开(公告)号：US12124702B2
公开(公告)日：2024-10-22
申请号：US17941092
申请日：2022-09-09
发明人： Hyunkook Park , Sara Choi
IPC分类号： G06F3/06
CPC分类号： G06F3/0611 , G06F3/0629 , G06F3/0679
摘要： A semiconductor memory device including: first and second memory cells storing multi-bit data; a first word line coupled to the first memory cell; and a second word line connected to the second memory cell and adjacent to the first word line; wherein a period in which a first word line voltage for reading data stored in the first memory cell is applied includes: a first period in which a first voltage level is applied to read first bit data from the multi-bit data stored in the first memory cell; a second period having a second voltage level lower than the first voltage level; and a third period in which a third voltage level higher than the second voltage level is applied to read second bit data from the multi-bit data stored in the first memory cell, wherein in the second period, the second word line is in a floating state.
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公开(公告)号：US20230162795A1
公开(公告)日：2023-05-25
申请号：US17881352
申请日：2022-08-04
发明人： Sara Choi , Hyunkook Park
CPC分类号： G11C16/08 , G11C16/0483 , G11C16/20 , G11C16/26
摘要： A memory device and an operating method thereof adjust a slope of a word line voltage. The memory device includes a memory cell array including a plurality of cell strings, a voltage generating circuit configured to generate a word line voltage provided to a plurality of word lines, and a control logic configured to output a slope control signal adjusting a voltage level variation characteristic of the word line voltage provided from the voltage generating circuit, wherein, during a prepulse period of a read operation of the memory device, a slope of a first word line voltage provided to an edge group including one or more word lines, the edge group adjacent to a string selection line is greater than a slope of a second word line voltage provided to a center group including one or more word lines in a center region.
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3.发明公开公开(公告)号：US20230140995A1
公开(公告)日：2023-05-11
申请号：US17941092
申请日：2022-09-09
发明人： Hyunkook Park , Sara Choi
IPC分类号： G06F3/06
CPC分类号： G06F3/0611 , G06F3/0679 , G06F3/0629
摘要： A semiconductor memory device including: first and second memory cells storing multi-bit data; a first word line coupled to the first memory cell; and a second word line connected to the second memory cell and adjacent to the first word line; wherein a period in which a first word line voltage for reading data stored in the first memory cell is applied includes: a first period in which a first voltage level is applied to read first bit data from the multi-bit data stored in the first memory cell; a second period having a second voltage level lower than the first voltage level; and a third period in which a third voltage level higher than the second voltage level is applied to read second bit data from the multi-bit data stored in the first memory cell, wherein in the second period, the second word line is in a floating state.
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