公开(公告)号：US20240412789A1

公开(公告)日：2024-12-12

申请号：US18607850

申请日：2024-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taewan Kim ,  Hyunkook Park

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C16/30

Abstract: The present disclosure relates to methods of operating non-volatile memory devices. An example read operation method of a non-volatile memory device includes applying a first read voltage, generated from a voltage generator, to a selected wordline, performing a first sensing node develop operation associated with the first read voltage, and performing a first sensing operation associated with the first read voltage. While the first sensing node develop operation is performed, the voltage generator generates a second read voltage based on the selected wordline being disconnected from the voltage generator and thereby being floated.

公开(公告)号：US12176036B2

公开(公告)日：2024-12-24

申请号：US17881352

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sara Choi ,  Hyunkook Park

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/20 ,  G11C16/26

Abstract: A memory device and an operating method thereof adjust a slope of a word line voltage. The memory device includes a memory cell array including a plurality of cell strings, a voltage generating circuit configured to generate a word line voltage provided to a plurality of word lines, and a control logic configured to output a slope control signal adjusting a voltage level variation characteristic of the word line voltage provided from the voltage generating circuit, wherein, during a prepulse period of a read operation of the memory device, a slope of a first word line voltage provided to an edge group including one or more word lines, the edge group adjacent to a string selection line is greater than a slope of a second word line voltage provided to a center group including one or more word lines in a center region.

公开(公告)号：US12124702B2

公开(公告)日：2024-10-22

申请号：US17941092

申请日：2022-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunkook Park ,  Sara Choi

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/0679

Abstract: A semiconductor memory device including: first and second memory cells storing multi-bit data; a first word line coupled to the first memory cell; and a second word line connected to the second memory cell and adjacent to the first word line; wherein a period in which a first word line voltage for reading data stored in the first memory cell is applied includes: a first period in which a first voltage level is applied to read first bit data from the multi-bit data stored in the first memory cell; a second period having a second voltage level lower than the first voltage level; and a third period in which a third voltage level higher than the second voltage level is applied to read second bit data from the multi-bit data stored in the first memory cell, wherein in the second period, the second word line is in a floating state.

公开(公告)号：US09685237B2

公开(公告)日：2017-06-20

申请号：US15189136

申请日：2016-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunkook Park ,  Yeongtaek Lee ,  Daeseok Byeon

IPC: G11C7/12 ,  G11C8/08 ,  G11C5/06 ,  G11C16/28 ,  H03K5/08 ,  H03K5/24 ,  G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C13/00 ,  G11C7/06 ,  G11C5/14

CPC classification number: G11C16/28 ,  G11C5/147 ,  G11C7/067 ,  G11C7/12 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C2013/0054 ,  H03K5/08 ,  H03K5/24

Abstract: Disclosed is a driver circuit. The driver circuit includes a clamp transistor, a comparison voltage transistor, an amplification transistor, a bias transistor, and a charge circuit. The comparison voltage is configured to provide a comparison voltage. The amplification transistor includes an amplification gate connected to a first node of the clamp transistor, a first amplification node configured to receive the comparison voltage, and a second amplification node connected to a gate of the clamp transistor. The bias transistor is configured to supply a bias voltage. The charge circuit is at least one of configured to drain a current from the first node through the clamp transistor and configured to supply a current to the first node through the clamp transistor.

公开(公告)号：US11908533B2

公开(公告)日：2024-02-20

申请号：US17727762

申请日：2022-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunkook Park

IPC: G11C16/00 ,  G11C16/34 ,  G11C16/08 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/32

Abstract: Disclosed is an operation method of a memory device which includes floating a first driving line corresponding to a first word line from the first word line and precharging the first driving line with a first voltage, floating the first driving line from the first voltage to sense a first voltage variation of the first driving line, storing the first voltage variation in a first capacitor, electrically connecting the first driving line to the first word line and precharging the first driving line and the first word line with the first voltage, floating the first driving line and the first word line from the first voltage to sense a second voltage variation of the first driving line and the first word line, and outputting a first detection signal corresponding to a first leakage current through the first word line based on the first voltage variation and the second voltage variation.

公开(公告)号：US20240379164A1

公开(公告)日：2024-11-14

申请号：US18602636

申请日：2024-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woosul SHIN ,  Sungwon Yun ,  Hyunkook Park ,  Hyunjun Yoon

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/34

Abstract: A method of programming data in a nonvolatile memory device includes setting a state ordering to a first state ordering, the state ordering representing a relationship between a plurality of states and data values of multi-bit data, performing, based on the first state ordering, a program operation on target memory cells of the plurality of memory cells, swapping the state ordering from the first state ordering to a second state ordering different from the first state ordering, performing, based on the second state ordering, the program operation on the target memory cells, re-swapping the state ordering from the second state ordering to the first state ordering, and performing, based on the first state ordering, the program operation on the target memory cells. Each memory cell of a plurality of memory cells of the nonvolatile memory device is programmed to have one of the plurality of states.

公开(公告)号：US20230162795A1

公开(公告)日：2023-05-25

申请号：US17881352

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sara Choi ,  Hyunkook Park

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/20 ,  G11C16/26

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/20 ,  G11C16/26

Abstract: A memory device and an operating method thereof adjust a slope of a word line voltage. The memory device includes a memory cell array including a plurality of cell strings, a voltage generating circuit configured to generate a word line voltage provided to a plurality of word lines, and a control logic configured to output a slope control signal adjusting a voltage level variation characteristic of the word line voltage provided from the voltage generating circuit, wherein, during a prepulse period of a read operation of the memory device, a slope of a first word line voltage provided to an edge group including one or more word lines, the edge group adjacent to a string selection line is greater than a slope of a second word line voltage provided to a center group including one or more word lines in a center region.

公开(公告)号：US20230140995A1

公开(公告)日：2023-05-11

申请号：US17941092

申请日：2022-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunkook Park ,  Sara Choi

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0679 ,  G06F3/0629

Abstract: A semiconductor memory device including: first and second memory cells storing multi-bit data; a first word line coupled to the first memory cell; and a second word line connected to the second memory cell and adjacent to the first word line; wherein a period in which a first word line voltage for reading data stored in the first memory cell is applied includes: a first period in which a first voltage level is applied to read first bit data from the multi-bit data stored in the first memory cell; a second period having a second voltage level lower than the first voltage level; and a third period in which a third voltage level higher than the second voltage level is applied to read second bit data from the multi-bit data stored in the first memory cell, wherein in the second period, the second word line is in a floating state.