公开(公告)号：US11989459B2

公开(公告)日：2024-05-21

申请号：US18073079

申请日：2022-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongjun Jin ,  Yongjae Lee ,  Seunghan Kim ,  Hyoungjoo Kim

IPC: G06F3/06 ,  G11C29/10 ,  G11C29/56

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0673 ,  G11C29/10 ,  G11C29/56004

Abstract: A semiconductor memory device includes a test pattern data storage configured to store test write pattern data in response to a register write command and a register address and output test read pattern data in response to a test read command and a test pattern data selection signal during a test operation, a memory cell array including a plurality of memory cells and configured to generate read data, a read path unit configured to generate n read data, by serializing the read data, and a test read data generation unit configured to generate n test read data, by comparing the test read pattern data with each of the n read data, generated at a first data rate, and generate the n test read data, at a second data rate lower than the first data rate, during the test operation.

公开(公告)号：US12119048B2

公开(公告)日：2024-10-15

申请号：US17964092

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghan Kim ,  Gunhee Cho

IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G11C11/4082 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096

Abstract: A semiconductor memory device includes a data input/output (I/O) buffer, a data first-in/first-out (FIFO) circuit, an address comparing circuit. The data I/O buffer provides a memory cell array with write data. The data FIFO circuit includes plurality of data FIFO buffers which store read data that is read from the memory cell array in each of a plurality of read operations. The data FIFO circuit outputs data stored in one of the plurality of data FIFO buffers based on a plurality of sub matching signals. The address comparing circuit sequentially stores previous addresses accompanied by first commands designating the plurality of read operations and generates the plurality of sub matching signals based on a comparison of the previous addresses and a present address accompanied by a second command designating a present read operation.

公开(公告)号：US11520528B2

公开(公告)日：2022-12-06

申请号：US17375168

申请日：2021-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongjun Jin ,  Yongjae Lee ,  Seunghan Kim ,  Hyoungjoo Kim

IPC: G06F3/06 ,  G11C29/56 ,  G11C29/10

Abstract: A semiconductor memory device includes a test pattern data storage configured to store test write pattern data in response to a register write command and a register address and output test read pattern data in response to a test read command and a test pattern data selection signal during a test operation, a memory cell array including a plurality of memory cells and configured to generate read data, a read path unit configured to generate n read data, by serializing the read data, and a test read data generation unit configured to generate n test read data, by comparing the test read pattern data with each of the n read data, generated at a first data rate, and generate the n test read data, at a second data rate lower than the first data rate, during the test operation.

公开(公告)号：US20250014634A1

公开(公告)日：2025-01-09

申请号：US18887410

申请日：2024-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghan Kim ,  Gunhee Cho

IPC: G11C11/4093 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096

Abstract: A semiconductor memory device includes a data input/output (I/O) buffer, a data first-in/first-out (FIFO) circuit, an address comparing circuit. The data I/O buffer provides a memory cell array with write data. The data FIFO circuit includes plurality of data FIFO buffers which store read data that is read from the memory cell array in each of a plurality of read operations. The data FIFO circuit outputs data stored in one of the plurality of data FIFO buffers based on a plurality of sub matching signals. The address comparing circuit sequentially stores previous addresses accompanied by first commands designating the plurality of read operations and generates the plurality of sub matching signals based on a comparison of the previous addresses and a present address accompanied by a second command designating a present read operation.

公开(公告)号：US20230335181A1

公开(公告)日：2023-10-19

申请号：US17964092

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghan Kim ,  Gunhee Cho

IPC: G11C11/4093 ,  G11C11/408

CPC classification number: G11C11/4093 ,  G11C11/4082

Abstract: A semiconductor memory device includes a data input/output (I/O) buffer, a data first-in/first-out (FIFO) circuit, an address comparing circuit. The data I/O buffer provides a memory cell array with write data. The data FIFO circuit includes plurality of data FIFO buffers which store read data that is read from the memory cell array in each of a plurality of read operations. The data FIFO circuit outputs data stored in one of the plurality of data FIFO buffers based on a plurality of sub matching signals. The address comparing circuit sequentially stores previous addresses accompanied by first commands designating the plurality of read operations and generates the plurality of sub matching signals based on a comparison of the previous addresses and a present address accompanied by a second command designating a present read operation.