公开(公告)号：US20190372581A1

公开(公告)日：2019-12-05

申请号：US16377460

申请日：2019-04-08

Applicant: Samsung Electronics Co., Ltd

Inventor： ILHOON JANG ,  Seung-Tak Ryu ,  Hyungjong Ko ,  Miyoung Kim ,  Seungyeob Baek ,  Min-Jae Seo ,  Jaekeun Lee ,  Michael Choi

IPC: H03M1/08 ,  H03M1/46 ,  H03M3/00

Abstract: An electronic circuit includes an analog to digital converter (ADC) and a noise coupling filter. The ADC generates a digital output signal based on a first analog signal and a second analog signal. The noise coupling filter generates the second analog signal to be fed back for an input to the ADC, based on a first quantization error signal associated with converting the first analog signal to the digital output signal. The noise coupling filter performs noise shaping on a digital error signal derived from the quantization error signal and generates the second analog signal from a result of the noise shaping, using a clock in the digital domain.

公开(公告)号：US11757462B2

公开(公告)日：2023-09-12

申请号：US17675342

申请日：2022-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyochul Shin ,  Seungyeob Baek ,  Sungno Lee ,  Heechang Hwang ,  Michael Choi

IPC: H03M1/10 ,  H03L7/081 ,  H04B1/16 ,  H04L25/03 ,  H04L1/00

CPC classification number: H03M1/1014 ,  H03L7/0812 ,  H04B1/16 ,  H04L1/0071 ,  H04L25/03012

Abstract: An analog-to-digital conversion circuit includes; a first analog-to-digital converter (ADC), a second ADC and a third ADC collectively configured to perform conversion operations according to a time-interleaving technique, and a timing calibration circuit configured to calculate correlation values and determine differences between the correlation values using first samples generated by the first ADC, second samples generated by the second ADC, and third samples generated by the third ADC during sampling periods, wherein the timing calibration circuit is further configured to control a phase of a clock signal applied to the second ADC in response to a change in absolute value related to the differences generated during the sampling periods.

公开(公告)号：US20250125812A1

公开(公告)日：2025-04-17

申请号：US18667343

申请日：2024-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jejoong Woo ,  Jaewoo Park ,  Seungyeob Baek ,  Myoungbo Kwak ,  Junghwan Choi

IPC: H03M1/00 ,  H03M1/12

Abstract: An example semiconductor device includes a plurality of analog-to-digital converters (ADCs) configured to receive an analog signal from at least one amplifier connected to a pad, and a logic circuit configured to control the plurality of ADCs. The logic circuit is configured to activate first active ADCs, among the plurality of ADCs, in a first operating mode, and to activate second active ADCs, among the plurality of ADCs, in a second operating mode different from the first operating mode. A first latency required for the first active ADCs to receive the analog signal and to output a first digital signal is longer than a second latency required for the second active ADCs to receive the analog signal and to output a second digital signal.

公开(公告)号：US10778239B2

公开(公告)日：2020-09-15

申请号：US16377460

申请日：2019-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilhoon Jang ,  Seung-Tak Ryu ,  Hyungjong Ko ,  Miyoung Kim ,  Seungyeob Baek ,  Min-Jae Seo ,  Jaekeun Lee ,  Michael Choi

IPC: H03M1/08 ,  H03M3/00 ,  H03M1/46

Abstract: An electronic circuit includes an analog to digital converter (ADC) and a noise coupling filter. The ADC generates a digital output signal based on a first analog signal and a second analog signal. The noise coupling filter generates the second analog signal to be fed back for an input to the ADC, based on a first quantization error signal associated with converting the first analog signal to the digital output signal. The noise coupling filter performs noise shaping on a digital error signal derived from the quantization error signal and generates the second analog signal from a result of the noise shaping, using a clock in the digital domain.