公开(公告)号：US20230291412A1

公开(公告)日：2023-09-14

申请号：US17974703

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungjun Roh ,  Jaewoo Park ,  Myoungbo Kwak ,  Jejoong Woo ,  Junghwan Choi

IPC: H03M1/18 ,  H03M1/48 ,  H03M1/12

CPC classification number: H03M1/186 ,  H03M1/121 ,  H03M1/48

Abstract: An electronic device which may include an analog-to-digital converter circuit that converts a level of an input signal to digital input values in response to a clock signal, an oscillator that generates the clock signal, a first equalization circuit that generates digital output signals by equalizing the digital input values, a first phase detector circuit that detects phases of the digital output signals and generates digital phase values, a loop filter that generates a first digital output value based on the digital phase values, a second equalization circuit that generates digital intermediate values by equalizing the digital input values, and a second phase detector circuit that detects phases of the digital intermediate values and to generate a second digital output value. The oscillator may adjust a frequency of the clock signal based on the first digital output value and the second digital output value.

公开(公告)号：US20250125812A1

公开(公告)日：2025-04-17

申请号：US18667343

申请日：2024-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jejoong Woo ,  Jaewoo Park ,  Seungyeob Baek ,  Myoungbo Kwak ,  Junghwan Choi

IPC: H03M1/00 ,  H03M1/12

Abstract: An example semiconductor device includes a plurality of analog-to-digital converters (ADCs) configured to receive an analog signal from at least one amplifier connected to a pad, and a logic circuit configured to control the plurality of ADCs. The logic circuit is configured to activate first active ADCs, among the plurality of ADCs, in a first operating mode, and to activate second active ADCs, among the plurality of ADCs, in a second operating mode different from the first operating mode. A first latency required for the first active ADCs to receive the analog signal and to output a first digital signal is longer than a second latency required for the second active ADCs to receive the analog signal and to output a second digital signal.

公开(公告)号：US12176912B2

公开(公告)日：2024-12-24

申请号：US17974703

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungjun Roh ,  Jaewoo Park ,  Myoungbo Kwak ,  Jejoong Woo ,  Junghwan Choi

IPC: H03M1/18 ,  H03M1/12 ,  H03M1/48 ,  H03M1/10

Abstract: An electronic device which may include an analog-to-digital converter circuit that converts a level of an input signal to digital input values in response to a clock signal, an oscillator that generates the clock signal, a first equalization circuit that generates digital output signals by equalizing the digital input values, a first phase detector circuit that detects phases of the digital output signals and generates digital phase values, a loop filter that generates a first digital output value based on the digital phase values, a second equalization circuit that generates digital intermediate values by equalizing the digital input values, and a second phase detector circuit that detects phases of the digital intermediate values and to generate a second digital output value. The oscillator may adjust a frequency of the clock signal based on the first digital output value and the second digital output value.