公开(公告)号：US09853048B2

公开(公告)日：2017-12-26

申请号：US15226329

申请日：2016-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Jeong Kim ,  O Ik Kwon ,  Jong Kyoung Park ,  Su Jee Sunwoo

IPC: H01L29/76 ,  H01L29/788 ,  H01L27/11582 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/311 ,  H01L27/11575

CPC classification number: H01L27/11582 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L27/11565 ,  H01L27/11575

Abstract: A memory device includes a plurality of gate electrode layers, an interlayer insulating layer, a plurality of contact plugs, and at least one contact insulating layer. The gate electrode layers extend in a first direction and have different lengths to form a step structure. The interlayer insulating layer is on the gate electrode layers. The contact plugs are connected to the gate electrode layers through the interlayer insulating layer. The at least one contact insulating layer is within the interlayer insulating layer and surrounds one or more of the contact plugs. The at least one contact insulating layer extends in the first direction.