公开(公告)号：US20220238672A1

公开(公告)日：2022-07-28

申请号：US17578981

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Taein KIM ,  Youngtek OH ,  Suhyeong LEE

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/51 ,  H01L27/11582

Abstract: A vertical NAND flash memory device and a method of manufacturing the same are provided. The vertical NAND flash memory device includes a charge trap layer arranged on an inner wall of a channel hole vertically formed on a substrate. The charge trap layer includes nanostructures distributed in a base. The nanostructures may include a material having a trap density of about 1×1019 cm−3 to about 10×1019 cm−3, and the base may include a material having a conduction band offset (CBO) of about 0.5 eV to about 3.5 eV with respect to the material included in the nanostructures.

公开(公告)号：US20210074719A1

公开(公告)日：2021-03-11

申请号：US16853838

申请日：2020-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghwan LEE ,  Suhyeong LEE ,  Ju-Young LIM ,  Daehyun JANG ,  Sanghoon JEONG

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

公开(公告)号：US20210151461A1

公开(公告)日：2021-05-20

申请号：US16993345

申请日：2020-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunil SHIM ,  Suhyeong LEE ,  Taisoo LIM

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/28 ,  H01L27/1157

Abstract: A semiconductor device includes gate layers stacked on a substrate in a first direction perpendicular to an upper surface of the substrate, and channel structures penetrating the gate layers and extending in the first direction, each of the channel structures includes first dielectric layers on side surfaces of the gate layers, respectively, and spaced apart from each other in the first direction, electric charge storage layers on side surfaces of the first dielectric layers, respectively, and spaced apart from each other in the first direction, a second dielectric layer extending perpendicularly to the substrate to conform to side surfaces of the electric change storage layers, and a channel layer extending perpendicularly, and each of the first dielectric layers has a first maximum length, and each of the electric charge storage layers has a second maximum length greater than the first maximum length in the first direction.

公开(公告)号：US20220238552A1

公开(公告)日：2022-07-28

申请号：US17718676

申请日：2022-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghwan LEE ,  Suhyeong LEE ,  Ju-Young LIM ,  Daehyun JANG ,  Sanghoon JEONG

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11529

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.