公开(公告)号：US20240221834A1

公开(公告)日：2024-07-04

申请号：US18357407

申请日：2023-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoseok HEO ,  Hyungyung KIM ,  Seungdam HYUN ,  Kyunghun KIM ,  Seungyeul YANG ,  Gukhyon YON ,  Minhyun LEE ,  Seokhoon CHOI

IPC: G11C16/04 ,  H10B43/27

CPC classification number: G11C16/0483 ,  H10B43/27

Abstract: A vertical non-volatile memory device and an electronic apparatus including the vertical non-volatile memory device are provided. The vertical non-volatile memory device includes a pillar, a channel layer surrounding a side surface of the pillar, a charge tunneling layer surrounding a side surface of the channel layer, a charge trap layer surrounding a side surface of the charge tunneling layer and including an amorphous oxynitride, a charge blocking layer surrounding a side surface of the charge trap layer, and a plurality of separation layers and a plurality of gate electrodes surrounding a side surface of the charge blocking layer and alternately arranged along the side surface of the charge blocking layer.

公开(公告)号：US20230272554A1

公开(公告)日：2023-08-31

申请号：US18298692

申请日：2023-04-11

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Changseok LEE ,  Hyeonsuk SHIN ,  Hyeonjin SHIN ,  Seokmo HONG ,  Minhyun LEE ,  Seunggeol NAM ,  Kyungyeol MA

IPC: C30B29/38 ,  H01L21/02

CPC classification number: C30B29/38 ,  H01L21/02172 ,  H01L21/02252 ,  H01L21/02293

Abstract: A boron nitride layer and a method of fabricating the same are provided. The boron nitride layer includes a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

公开(公告)号：US20230079680A1

公开(公告)日：2023-03-16

申请号：US17829679

申请日：2022-06-01

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Keunwook SHIN ,  Kibum KIM ,  Kyung-Eun BYUN ,  Hyeonjin SHIN ,  Minhyun LEE ,  Changseok LEE

IPC: C01B32/186 ,  C01B32/188 ,  H01L29/41 ,  H01L29/40

Abstract: Provided are a wiring including a graphene layer and a method of manufacturing the wiring. The method may include growing a graphene layer on a substrate and doping the graphene layer with a metal. The graphene layer may be grown using a plasma of a hydrocarbon at a temperature of about 200° C. to about 600° C. by plasma enhanced chemical vapor deposition (PECVD).

公开(公告)号：US20220415801A1

公开(公告)日：2022-12-29

申请号：US17902319

申请日：2022-09-02

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeonjin SHIN ,  Minhyun LEE ,  Changseok LEE ,  Hyeonsuk SHIN ,  Seokmo HONG

IPC: H01L23/532 ,  H01L23/522

Abstract: An interconnect structure and an electronic apparatus including the interconnect structure are provided. The interconnect structure includes a conductive layer; a dielectric layer configured to surround at least a part of the conductive layer; and a diffusion barrier layer disposed between the conductive layer and the dielectric layer and configured to limit and/or prevent a conductive material of the conductive layer from diffusing into the dielectric layer, and at least one of the dielectric layer and the diffusion barrier layer includes a boron nitride layer of a low dielectric constant.

公开(公告)号：US20210305378A1

公开(公告)日：2021-09-30

申请号：US17014127

申请日：2020-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Hyeonjin SHIN ,  Minseok YOO ,  Minhyun LEE

IPC: H01L29/41 ,  H01L29/417 ,  H01L29/24 ,  H01L29/06 ,  H01L29/45 ,  H01L29/786 ,  H01L29/66

Abstract: Provided are two-dimensional material (2D)-based wiring conductive layer contact structures, electronic devices including the same, and methods of manufacturing the electronic devices. A 2D material-based field effect transistor includes a substrate; first to third 2D material layers on the substrate; an insulating layer on the first 2D material layer; a source electrode on the second 2D material layer; a drain electrode on the third 2D material layer; and a gate electrode on the insulating layer. The first 2D material layer is configured to exhibit semiconductor characteristics, and the second and third 2D material layers are metallic 2D material layers. The first 2D material layer may include a first channel layer of a 2D material and a second channel layer of a 2D material. The first 2D material layer may partially overlap the second and third 2D material layers.

公开(公告)号：US20210296445A1

公开(公告)日：2021-09-23

申请号：US17203010

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/24

Abstract: A field effect transistor includes a substrate, a source electrode and a drain electrode on the substrate and apart from each other in a first direction, a plurality of channel layers, a gate insulating film surrounding each of the plurality of channel layers, and a gate electrode surrounding the gate insulating film. Each of the plurality of channel layers has ends contacting the source electrode and the drain electrode. The plurality of channel layers are spaced apart from each other in a second direction away from the substrate. The plurality of channel layers include a 2D semiconductor material.

公开(公告)号：US20210288171A1

公开(公告)日：2021-09-16

申请号：US17201485

申请日：2021-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/24 ,  H01L27/092

Abstract: A vertical type transistor includes: a substrate; a first source/drain electrode layer provided on the substrate; a second source/drain electrode layer provided above the first source/drain electrode layer; a first gate electrode layer provided between the first and second source/drain electrode layers; a first gate insulating film passing through the first gate electrode layer; a hole passing through the second source/drain electrode layer, the first gate insulating film, and the first source/drain electrode layer; and a first channel layer provided on a lateral side of the hole, wherein the first channel layer may include a 2D semiconductor.

公开(公告)号：US20240215249A1

公开(公告)日：2024-06-27

申请号：US18322365

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghun KIM ,  Sunho KIM ,  Seyun KIM ,  Hyungyung KIM ,  Seungyeul YANG ,  Gukhyon YON ,  Minhyun LEE ,  Seokhoon CHOI ,  Hoseok HEO

IPC: H10B43/35 ,  H10B43/27

CPC classification number: H10B43/35 ,  H10B43/27

Abstract: A vertical NAND flash memory device may include a plurality of cell arrays. Each of the plurality of cell arrays may include a channel layer, a charge trap layer on the channel layer, and a plurality of gate electrodes on the charge trap layer. The charge trap layer may include silicon oxynitride comprising a metal. The metal may include at least one of Ga or In.

公开(公告)号：US20210226010A1

公开(公告)日：2021-07-22

申请号：US17111965

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Hyeonjin SHIN

IPC: H01L29/10 ,  H01L29/36 ,  H01L29/423

Abstract: A transistor including at least one two-dimensional (2D) channel is disclosed. A transistor according to some example embodiments includes first to third electrodes separated from each other, and a channel layer that is in contact with the first and second electrodes, parallel to the third electrode, and includes at least one 2D channel. The at least one 2D channel includes at least two regions having different doping concentrations. A transistor according to some example embodiments includes: first to third electrodes separated from each other; a 2D channel layer that is in contact with the first and second electrodes and parallel to the third electrode; a first doping layer disposed under the 2D channel layer corresponding to the first electrode; and a second doping layer disposed under the 2D channel layer corresponding to the second electrode, wherein the first and second doping layers contact the 2D channel layer.

公开(公告)号：US20210223683A1

公开(公告)日：2021-07-22

申请号：US17223568

申请日：2021-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Hyeonjin SHIN ,  Seongjun JEONG ,  Seongjun PARK

IPC: G03F1/62 ,  G03F1/64

Abstract: A pellicle configured to protecting a photomask from external contaminants may include a metal catalyst layer and a pellicle membrane including a 2D material on the metal catalyst layer, wherein the metal catalyst layer supports edge regions of the pellicle membrane and does not support a central region of the pellicle membrane. The metal catalyst layer may be on a substrate, such that the substrate and the metal catalyst layer collectively support the edge region of the pellicle membrane and do not support the central region of the pellicle membrane. The pellicle may be formed based on growing the 2D material on the metal catalyst layer and etching an inner region of the metal catalyst layer that supports the central region of the formed pellicle membrane.