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    METHOD OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    1.
    发明申请
    METHOD OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200266209A1

    公开(公告)日：2020-08-20

    申请号：US16863381

    申请日：2020-04-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Han Geun YU ,  Daehyun JANG

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/033 ,  H01L27/11568 ,  H01L21/311

    Abstract: Methods of fabricating a three-dimensional semiconductor memory device are provided. A method may include forming a mold structure on a substrate including channel regions and a non-channel region between the channel regions, and forming, on the mold structure, a multilayered mask layer including a first mask layer, an etch stop layer, and a second mask layer that are sequentially stacked. The multilayered mask layer may include mask holes exposing the mold structure in the channel regions, dummy mask holes exposing the first mask layer in the non-channel region, and buffer spacers covering sidewalls of the second mask layer exposed by the mask holes and the dummy mask holes. The method may include etching the mold structure using the multilayered mask layer as an etch mask to form channel holes in the channel regions.

    METHOD OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR DEVICES
    2.
    发明申请
    METHOD OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20180330948A1

    公开(公告)日：2018-11-15

    申请号：US15808993

    申请日：2017-11-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yong-Hyun KWON ,  Daehyun JANG

    IPC: H01L21/033 ,  H01L21/311 ,  H01L21/28

    CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/31144 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/40117

    Abstract: A method of fabricating a three-dimensional semiconductor device comprises stacking first hardmask layers and second hardmask layers on a lower layer including a pattern region and a buffer region adjacent to the pattern region, the second hardmask layers and the first hardmask layers for forming a first hardmask pattern and a second hardmask pattern, patterning the second hardmask layer to form the second hardmask pattern including a plurality of first mask holes on the pattern region and at least one recess on the buffer region, the plurality of first mask holes exposing the first hardmask layer, and etching the first hardmask layer using the second hardmask pattern as an etch mask to form the first hardmask pattern including a plurality of etch mask holes on the pattern region and at least one buffer mask hole on the buffer region, the plurality of etch mask holes exposing a top surface of the lower layer, the at least one buffer mask hole having a bottom surface spaced apart from the top surface of the lower layer.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME 审中-公开
    半导体存储器件及其形成方法

    公开(公告)号：US20140162440A1

    公开(公告)日：2014-06-12

    申请号：US14082657

    申请日：2013-11-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Ho Kim ,  Daehyun JANG ,  Myoungbum LEE ,  Kihyun HWANG ,  Sangryol YANG ,  Yong-Hoon SON ,  Ju-Eun KIM ,  Sunghae LEE ,  Dongwoo KIM ,  JinGyun KIM

    IPC: H01L27/115 ,  H01L21/02

    CPC classification number: H01L27/11582 ,  H01L21/02675 ,  H01L21/30604 ,  H01L21/324 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/7926

    Abstract: Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.

    Abstract translation: 可以提供形成半导体器件的方法。 形成半导体器件的方法可以包括图案化第一和第二材料层以形成暴露衬底的第一穿透区域。 该方法可以包括在衬底上的第一至区域中以及在第一和第二材料层的侧壁上形成第一半导体层。 在一些实施例中，该方法可以包括形成填充第一半导体层上的第一通过区域的掩埋层。 在一些实施例中，该方法可以包括移除掩埋层的一部分以在第一和第二材料层的侧壁之间形成第二穿透区域。 此外，该方法可以包括在第二通过区域中形成第二半导体层。

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220238552A1

    公开(公告)日：2022-07-28

    申请号：US17718676

    申请日：2022-04-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seunghwan LEE ,  Suhyeong LEE ,  Ju-Young LIM ,  Daehyun JANG ,  Sanghoon JEONG

    IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11529

    Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

    SEMICONDUCTOR DEVICES
    6.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210098483A1

    公开(公告)日：2021-04-01

    申请号：US16890500

    申请日：2020-06-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seogoo KANG ,  Daehyun JANG ,  Jaeryong SIM ,  Jongseon AHN ,  Jeehoon HAN

    IPC: H01L27/11575 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11548

    Abstract: A semiconductor device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate; and a memory cell region including a second substrate on an upper portion of the first substrate, gate electrodes spaced apart from each other and vertically stacked on the second substrate, channel structures extending vertically through the gate electrodes to the second substrate, first separation regions penetrating through the gate electrodes between the channel structures and extending in one direction, and a second separation region extending vertically to penetrate through the second substrate from above and having a bent portion due to a change in width.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210074719A1

    公开(公告)日：2021-03-11

    申请号：US16853838

    申请日：2020-04-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seunghwan LEE ,  Suhyeong LEE ,  Ju-Young LIM ,  Daehyun JANG ,  Sanghoon JEONG

    IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

    Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

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