公开(公告)号：US20210091085A1

公开(公告)日：2021-03-25

申请号：US16850223

申请日：2020-04-16

申请人： Samsung Electronics Co., Ltd.

发明人： Sungmi YOON ,  Donghyun IM ,  Jooyub KIM ,  Juhyung WE ,  Namhoon LEE ,  Chunhyung CHUNG

IPC分类号： H01L27/108 ,  H01L29/06 ,  H01L21/762

摘要： A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.

公开(公告)号：US20220165608A1

公开(公告)日：2022-05-26

申请号：US17574665

申请日：2022-01-13

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Dong-Hyun IM ,  Kibum LEE ,  Daehyun KIM ,  Ju Hyung WE ,  Sungmi YOON

IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L21/02 ,  H01L27/108 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/146 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234

摘要： A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.

公开(公告)号：US20220037328A1

公开(公告)日：2022-02-03

申请号：US17210931

申请日：2021-03-24

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hyewon KIM ,  Juhyung WE ,  Sungmi YOON ,  Donghyun IM ,  Sangwoon LEE ,  Taiuk RIM ,  Kyosuk CHAE

IPC分类号： H01L27/108

摘要： A semiconductor device including a substrate including a recess; a gate insulation layer on a surface of the recess; a first gate pattern on the gate insulation layer and filling a lower portion of the recess; a second gate pattern on the first gate pattern in the recess and including a material having a work function different from a work function of the first gate pattern; a capping insulation pattern on the second gate pattern and filling an upper portion of the recess; a leakage blocking oxide layer on the gate insulation layer at an upper sidewall of the recess above an upper surface of the first gate pattern and contacting a sidewall of the capping insulation pattern; and impurity regions in the substrate and adjacent to the upper sidewall of the recess, each impurity region having a lower surface higher than the upper surface of the first gate pattern.

公开(公告)号：US20220189963A1

公开(公告)日：2022-06-16

申请号：US17685794

申请日：2022-03-03

申请人： Samsung Electronics Co., Ltd.

发明人： Sungmi YOON ,  Donghyun IM ,  Jooyub KIM ,  Juhyung WE ,  Namhoon LEE ,  Chunhyung CHUNG

IPC分类号： H01L27/108 ,  H01L21/762 ,  H01L29/06

摘要： A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.

公开(公告)号：US20220181457A1

公开(公告)日：2022-06-09

申请号：US17340667

申请日：2021-06-07

申请人： Samsung Electronics Co., Ltd.

发明人： Sungmi YOON ,  Jooyub KIM ,  Daehyun KIM ,  Juhyung WE ,  Donghyun IM ,  Chunhyung CHUNG

IPC分类号： H01L29/423 ,  H01L29/49 ,  H01L27/108

摘要： A semiconductor device may include a substrate including a recess, a gate insulation layer on a surface of the recess, an impurity barrier layer on a surface of the gate insulation layer to cover the surface of the gate insulation layer, a first gate pattern on impurity barrier layer to fill a lower portion of the recess, a second gate pattern on the first gate pattern in the recess, a capping insulation pattern on the second gate pattern to fill the recess, and impurity regions at the substrate adjacent to an upper sidewall of the recess. The impurity barrier layer may have a concentration of nitrogen higher than a concentration of nitrogen included in the gate insulation layer. The second gate pattern may include a material different from a material of the first gate pattern. A lower surface of the impurity regions may be higher than an upper surface of the first gate pattern. Thus, the semiconductor device may have good characteristics.

公开(公告)号：US20190296025A1

公开(公告)日：2019-09-26

申请号：US16023018

申请日：2018-06-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sungmi YOON ,  Chunhyung CHUNG

IPC分类号： H01L27/108 ,  H01L21/762 ,  H01L21/3205 ,  H01L21/321 ,  H01L29/06 ,  C23C16/44 ,  C23C16/02 ,  C23C16/24

摘要： Provided is a method for manufacturing a semiconductor device including: patterning a substrate to form a plurality of active patterns including two adjacent active patterns having a first trench therebetween; forming a semiconductor layer on the plurality of active patterns to cover the plurality of active patterns; forming a device isolation layer on the semiconductor layer to cover the semiconductor layer for oxidization and fill the first trench; patterning the device isolation layer and the plurality of active patterns so that a second trench intersecting the first trench is formed and the two active patterns protrudes from the device isolation layer in the second trench; and forming a gate electrode in the second trench. Here, a first thickness of the semiconductor layer covering a top surface of each of the two active patterns is greater than a second thickness of the semiconductor layer covering a bottom of the first trench.