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公开(公告)号:US20240061345A1
公开(公告)日:2024-02-22
申请号:US18207510
申请日:2023-06-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kibum LEE , Taesoo SHIN , Seulgi OK , Sungwook HWANG
IPC: G03F7/20
CPC classification number: G03F7/7065
Abstract: A method of detecting defects of a wafer including generating a composite wafer map comprising defect points by combining a plurality of wafer level maps generated by measuring the wafer according to the respective process operations; sorting the defect points according to defect clusters using positions of the defect points included in the composite wafer map; and detecting an initial process operation, from among the respective process operations, in which a defect occurred, using operation information, for each of the defect clusters.
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公开(公告)号:US20240127425A1
公开(公告)日:2024-04-18
申请号:US18195190
申请日:2023-05-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sungwook HWANG , Tae Soo SHIN , Seulgi OK , Kibum LEE
IPC: G06T7/00 , G01N23/2251 , G06T7/70
CPC classification number: G06T7/001 , G01N23/2251 , G06T7/70 , G01N2223/418 , G01N2223/6116 , G06T2207/10061 , G06T2207/20084 , G06T2207/20132 , G06T2207/30148
Abstract: A defect detection device includes: a memory configured to store a layout image indicating a circuit pattern and indicating a dummy pattern; and a controller comprising an artificial neural network configured to learn the layout image, the controller being configured to: determine, based on an inspection image obtained by photographing an area including a defect on a wafer, whether the defect is in a first area in which the circuit pattern is positioned or in a second area in which the dummy pattern is positioned, by using the artificial neural network, and determine a type of the defect based on whether the defect is positioned is in the first area or in the second area.
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公开(公告)号:US20250048717A1
公开(公告)日:2025-02-06
申请号:US18745614
申请日:2024-06-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hokyun AN , Kibum LEE , Jungmin CHO , Sunggyu CHOI
IPC: H01L21/8238 , H01L21/225 , H01L21/265 , H01L21/324
Abstract: A method of manufacturing a semiconductor device includes forming, on a substrate, a semiconductor material layer including germanium, forming a diffusion material layer in an upper portion of the substrate adjacent to the semiconductor material layer by performing a first heat treatment on the semiconductor material layer, removing the semiconductor material layer, recrystallizing the diffusion material layer by performing a second heat treatment on the diffusion material layer, and forming a fin-type structure by removing at least a portion of the substrate and at least a portion of the diffusion material layer. The diffusion material layer includes germanium diffused from the semiconductor material layer. A germanium concentration in the fin-type structure decreases from an upper surface of the fin-type structure toward a lower surface of the fin-type structure along a vertical direction perpendicular to a top surface of the substrate.
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公开(公告)号:US20220165608A1
公开(公告)日:2022-05-26
申请号:US17574665
申请日:2022-01-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dong-Hyun IM , Kibum LEE , Daehyun KIM , Ju Hyung WE , Sungmi YOON
IPC: H01L21/762 , H01L21/763 , H01L21/02 , H01L27/108 , H01L27/11556 , H01L27/11582 , H01L27/146 , H01L29/78 , H01L21/8238 , H01L21/8234
Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.
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