公开(公告)号：US20210399019A1

公开(公告)日：2021-12-23

申请号：US17316777

申请日：2021-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungjin Cho ,  Sungwon Shin ,  Euijoong Shin

IPC: H01L27/11597 ,  H01L29/51 ,  H01L27/1159 ,  H01L27/11592

Abstract: Semiconductor devices may include a stacked structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, a core region extending in the vertical direction in the stacked structure, a channel layer on a side surface of the core region and facing the gate electrodes and the interlayer insulating layers, a first dielectric layer, a data storage layer and a second dielectric layer, which are between the channel layer and the gate electrodes in order, and an anti-ferroelectric layer including a portion interposed between the first dielectric layer and a first gate electrode of the gate electrodes. The second dielectric layer may contact the channel layer. The anti-ferroelectric layer may be formed of an anti-ferroelectric material having a tetragonal phase.

公开(公告)号：US11744082B2

公开(公告)日：2023-08-29

申请号：US17316777

申请日：2021-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungjin Cho ,  Sungwon Shin ,  Euijoong Shin

IPC: H10B51/20 ,  H01L29/51 ,  H10B51/30 ,  H10B51/40 ,  H10B43/40 ,  H10B43/20 ,  H10B43/30

CPC classification number: H10B51/20 ,  H01L29/516 ,  H10B43/20 ,  H10B43/30 ,  H10B43/40 ,  H10B51/30 ,  H10B51/40

Abstract: Semiconductor devices may include a stacked structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, a core region extending in the vertical direction in the stacked structure, a channel layer on a side surface of the core region and facing the gate electrodes and the interlayer insulating layers, a first dielectric layer, a data storage layer and a second dielectric layer, which are between the channel layer and the gate electrodes in order, and an anti-ferroelectric layer including a portion interposed between the first dielectric layer and a first gate electrode of the gate electrodes. The second dielectric layer may contact the channel layer. The anti-ferroelectric layer may be formed of an anti-ferroelectric material having a tetragonal phase.

公开(公告)号：US11887936B2

公开(公告)日：2024-01-30

申请号：US17469952

申请日：2021-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyong Kim ,  Sungwon Shin ,  Seungmin Lee ,  Juyoung Lim ,  Wonseok Cho

IPC: H01L23/544 ,  H01L23/532 ,  H01L23/528 ,  H10B41/46

CPC classification number: H01L23/544 ,  H01L23/5283 ,  H01L23/53295 ,  H10B41/46

Abstract: A semiconductor device includes a first stack structure on a substrate, and a second stack structure on the first stack structure. A channel structure extends through the first stack structure and the second stack structure. A first auxiliary stack structure including a plurality of first insulating layers and a plurality of first mold layers are alternately stacked on the substrate. An alignment key extends into the first auxiliary stack structure and protrudes to a higher level than an uppermost end of the first stack structure. A second auxiliary stack structure is disposed on the first auxiliary stack structure and the alignment key, and includes a plurality of second insulating layers and a plurality of second mold layers alternately stacked. The second auxiliary stack structure includes a protrusion aligned with the alignment key.