公开(公告)号：US20240130122A1

公开(公告)日：2024-04-18

申请号：US18206785

申请日：2023-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin LEE ,  Daeyeong LEE ,  Sunyi LEE ,  Jaeho CHOI

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06541

Abstract: A three-dimensional semiconductor memory device may include a substrate, a stack including interlayer insulating layers and gate electrodes alternatingly stacked on the substrate, a dummy pad on a pad portion of each gate electrode, a source structure between the substrate and the stack, and first vertical channel structures that penetrate the stack and the source structure. The pad portions may include a first pad portion vertically overlapped with the dummy pad and a second pad portion horizontally overlapped with the dummy pad. The first and second pad portions may be spaced apart from the dummy pad, and one of the interlayer insulating layers may be interposed between the first pad portion and the dummy pad. The one of the interlayer insulating layers may extend continuously from a first portion to a second portion via a connection portion.