公开(公告)号：US20240061492A1

公开(公告)日：2024-02-22

申请号：US18180427

申请日：2023-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bumgyu PARK ,  Jonglae PARK ,  Choonghoon PARK ,  Daeyeong LEE ,  Jiyoung LEE ,  Hyunwook JOO

IPC: G06F1/3234 ,  G06F1/20

CPC classification number: G06F1/3275 ,  G06F1/206

Abstract: A processor includes a central processing unit (CPU) configured to drive a dynamic voltage and frequency scaling (DVFS) module, a memory hierarchy configured to store data for an operation of the CPU, and an activity monitoring unit (AMU) configured to generate microarchitecture information by monitoring performance of the CPU or monitoring traffic of a system bus connected to the memory hierarchy. The DVFS module is configured to determine a layer within the memory hierarchy in which a memory stall occurs using the microarchitecture information, and to increase a frequency in response to the determined layer being accessed.

公开(公告)号：US20240130122A1

公开(公告)日：2024-04-18

申请号：US18206785

申请日：2023-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin LEE ,  Daeyeong LEE ,  Sunyi LEE ,  Jaeho CHOI

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06541

Abstract: A three-dimensional semiconductor memory device may include a substrate, a stack including interlayer insulating layers and gate electrodes alternatingly stacked on the substrate, a dummy pad on a pad portion of each gate electrode, a source structure between the substrate and the stack, and first vertical channel structures that penetrate the stack and the source structure. The pad portions may include a first pad portion vertically overlapped with the dummy pad and a second pad portion horizontally overlapped with the dummy pad. The first and second pad portions may be spaced apart from the dummy pad, and one of the interlayer insulating layers may be interposed between the first pad portion and the dummy pad. The one of the interlayer insulating layers may extend continuously from a first portion to a second portion via a connection portion.

公开(公告)号：US20240086234A1

公开(公告)日：2024-03-14

申请号：US18196749

申请日：2023-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonglae Park ,  Eunok JO ,  Bumgyu PARK ,  Seyeong BYEON ,  Daeyeong LEE

IPC: G06F9/48

CPC classification number: G06F9/4881

Abstract: An electronic device includes: a plurality of processing cores and a memory including a plurality of task queues respectively corresponding to the plurality of processing cores and a plurality of task relation tables respectively corresponding to a plurality of tasks. Each of the plurality of task relation tables includes: one or more entries representing a mapping relationship between an identifier of a waker task that wakes up a wakee task, and an occurrence count that is a number of times the wakee task is woken up by the waker task. At least one of the plurality of processing cores is configured to: execute a scheduler, search for a task set includes related tasks, based on the plurality of task relation tables, store a subset of tasks of the task set in at least one of the plurality of task queues, and schedule the task set.