公开(公告)号：US20240306402A1

公开(公告)日：2024-09-12

申请号：US18375173

申请日：2023-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Takuya FUTATSUYAMA ,  Daeseok BYEON

IPC: H10B80/00 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3445 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: In some embodiments, a semiconductor memory device includes a peripheral circuit structure, and a first and a second cell array structure. The peripheral circuit structure includes a circuit board, a peripheral circuit on the circuit board, a first insulating layer, and a plurality of first bonding pads on the first insulating layer. The first cell array structure includes a first memory cell array, a first conductive plate structure, a second insulating layer, and pluralities of second and third bonding pads on the second insulating layer. The second cell array structure includes a second memory cell array, a second conductive plate structure, a third insulating layer, and a plurality of fourth bonding pads on the third insulating layer. The first cell array structure and the second cell array structure are sequentially stacked in a vertical direction on the peripheral circuit structure.

公开(公告)号：US20240284673A1

公开(公告)日：2024-08-22

申请号：US18583467

申请日：2024-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Takuya FUTATSUYAMA ,  Daeseok BYEON

IPC: H10B43/27 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H10B43/35 ,  H10B43/40 ,  H10B61/00 ,  H10B63/10

CPC classification number: H10B43/27 ,  H01L23/481 ,  H01L24/08 ,  H01L25/0657 ,  H10B43/35 ,  H10B43/40 ,  H01L2224/08145 ,  H01L2924/1438 ,  H10B61/20 ,  H10B63/10

Abstract: A memory device is disclosed. The memory device includes a first cell region including first memory strings, a second cell region attached to the first cell region and including second memory strings, and a peripheral circuit region attached to the first cell region and including a peripheral circuit configured to control the first and second memory strings, the first cell region including a low-level bit line electrically connected to the first memory strings, a low-level bonding pad provided between the peripheral circuit region and the first cell region, a low-level connection via connected to the low-level bonding pad, a high-level bonding pad provided between the first and second cell regions, the second cell region including a high-level bit line electrically connected to the second memory strings, and a high-level connection via connected to the high-level bonding pad and being laterally offset from the low-level connection via.