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    Semiconductor memory device with multiple sub-memory cell arrays and memory system including same
    2.
    发明授权
    Semiconductor memory device with multiple sub-memory cell arrays and memory system including same 有权
    具有多个子存储单元阵列的半导体存储器件和包括其的存储器系统

    公开(公告)号：US09384092B2

    公开(公告)日：2016-07-05

    申请号：US14300289

    申请日：2014-06-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dae Hyun Kim ,  Seung Jun Bae ,  Young Soo Sohn ,  Tae Young Oh ,  Won Jin Lee

    IPC: G11C29/42 ,  G06F11/10 ,  G11C7/08 ,  G11C7/06 ,  G11C29/54 ,  G11C11/4091 ,  G11C11/419

    CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G11C7/065 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/419

    Abstract: A semiconductor memory device includes; a memory cell array comprising a first sub-memory cell array storing first data having a first characteristic and a second sub-memory cell array storing second data having a second characteristic different from the first characteristic, a first peripheral circuit operatively associated with only the first sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the first sub-memory cell array, and a second peripheral circuit operatively associated with only the second sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the second sub-memory cell array.

    Abstract translation: 半导体存储器件包括： 存储单元阵列，包括存储具有第一特性的第一数据的第一子存储单元阵列和存储具有与第一特性不同的第二特性的第二数据的第二子存储单元阵列;第一外围电路， 子存储器单元阵列，以执行指向第一子存储单元阵列的目标存储单元的读取操作和写入操作中的至少一个，以及仅与第二子存储单元阵列可操作地相关联的第二外围电路， 执行指向第二子存储单元阵列的目标存储单元的读取操作和写入操作中的至少一个。

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