公开(公告)号：US20240194553A1

公开(公告)日：2024-06-13

申请号：US18374123

申请日：2023-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyoung KIM ,  Wonbin SHIN ,  Kiseok KIM ,  Jihye SHIM

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H10B80/00

CPC classification number: H01L23/3135 ,  H01L23/296 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/162 ,  H10B80/00 ,  H01L24/16 ,  H01L2224/08113 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/97 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/3511

Abstract: A semiconductor package includes a first chip including a first substrate, a first wiring layer on the first substrate, and a plurality of through-electrodes to be connected to the first wiring layer and protruding from a lower surface of the first substrate, a double gap-fill layer covering a side surface and a lower surface of the first chip and a protruding portion of the through-electrode and having a double layer structure, a second chip disposed on the first chip and the double gap-fill layer, including a second wiring layer and a second substrate on the second wiring layer, and bonded to the first chip by hybrid bonding, and a bump on a lower surface of the first chip and connected to the through-electrode.