公开(公告)号：US20220199511A1

公开(公告)日：2022-06-23

申请号：US17460745

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjung Jang ,  Chulyong Jang

IPC: H01L23/498 ,  H01L23/00

Abstract: A package substrate includes an insulating layer having a mounting surface; a wiring pattern extending in the insulating layer; and a chip bonding pad provided on the mounting surface of the insulating layer and connected to the wiring pattern, the chip bonding pad having a tapered shape in which a horizontal cross-sectional area thereof gradually decreases away from the mounting surface of the insulating layer in a vertical direction. A portion of the chip bonding pad closest to the mounting surface of the insulating layer has a horizontal length of about 20 micrometers (μm) to about 30 μm.

公开(公告)号：US11923286B2

公开(公告)日：2024-03-05

申请号：US17460745

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjung Jang ,  Chulyong Jang

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/16227

Abstract: A package substrate includes an insulating layer having a mounting surface; a wiring pattern extending in the insulating layer; and a chip bonding pad provided on the mounting surface of the insulating layer and connected to the wiring pattern, the chip bonding pad having a tapered shape in which a horizontal cross-sectional area thereof gradually decreases away from the mounting surface of the insulating layer in a vertical direction. A portion of the chip bonding pad closest to the mounting surface of the insulating layer has a horizontal length of about 20 micrometers (μm) to about 30 μm.

公开(公告)号：US20240006382A1

公开(公告)日：2024-01-04

申请号：US18311289

申请日：2023-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonjung Jang ,  Jungseok Ahn

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/481 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/293 ,  H01L24/81 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2225/06513

Abstract: The reliability of stacked semiconductor packages may be improved via a semiconductor package including a first semiconductor chip including through silicon vias (TSVs) with respective upper conductive pads electrically connected to the TSVs, a second semiconductor chip on the first semiconductor chip with lower conductive pads on a lower surface of the second semiconductor chip, conductive bumps between the upper conductive pads and the lower conductive pads, and an interlayer adhesive layer between the first semiconductor chip and the second semiconductor chip. An interlayer space is between the first semiconductor chip and the second semiconductor chip and overlaps the first semiconductor chip and the second semiconductor chip in a vertical direction. The encapsulant extends into the interlayer space.