公开(公告)号：US11705323B2

公开(公告)日：2023-07-18

申请号：US17078278

申请日：2020-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungseok Ahn ,  Unbyoung Kang ,  Chungsun Lee ,  Teakhoon Lee

IPC: H01L21/02 ,  H01L21/304 ,  B24B21/00 ,  B28D5/02 ,  B26D7/18 ,  H01L21/68

CPC classification number: H01L21/02021 ,  B24B21/002 ,  B26D7/18 ,  B28D5/02 ,  H01L21/304 ,  H01L21/68

Abstract: The wafer trimming device includes a chuck table configured to hold a target wafer via suction, thereby fixing the target wafer, a notch trimmer configured to trim a notch of the target wafer, and an edge trimmer configured to trim an edge of the target wafer. The notch trimmer includes a notch trimming blade configured to rotate about a rotation axis perpendicular to a circumferential surface of the target wafer. The edge trimmer includes an edge trimming blade configured to rotate about a rotation axis parallel to the circumferential surface of the target wafer.

公开(公告)号：US20230075665A1

公开(公告)日：2023-03-09

申请号：US17875983

申请日：2022-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkyun Kwon ,  Jungseok Ahn ,  Kuyoung Kim

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor package includes a substrate, a plurality of semiconductor devices stacked on the substrate, an under-fill fillet on side surfaces of the plurality of semiconductor devices, and a molding resin surrounding the plurality of semiconductor devices. An uppermost end of the under-fill fillet includes a planar surface coplanar with an upper surface of a periphery of an uppermost semiconductor device among the plurality of semiconductor devices, and the molding resin completely covers the planar surface.

公开(公告)号：US20240063186A1

公开(公告)日：2024-02-22

申请号：US18301541

申请日：2023-04-17

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： SEYONG LEE ,  Jungseok Ahn

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/73 ,  H01L24/16 ,  H01L2225/06513 ,  H01L2224/0401 ,  H01L2224/06515 ,  H01L2224/05647 ,  H01L2224/05624 ,  H01L2224/05684 ,  H01L2224/05655 ,  H01L2224/0568 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2224/05671 ,  H01L2224/05611 ,  H01L2224/05666 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/16145

Abstract: A semiconductor package includes a first semiconductor chip including a substrate having a first upper surface and a first lower surface opposite thereto. The substrate has a central region and corner regions surrounding the central region. A plurality of through electrodes passes through the central region. A bonding pad is electrically connected to the through electrode and has a first height. A plurality of dummy pads respectively extend from the first upper surface on the corner regions of the substrate and have a second height that is higher than the first height. A second semiconductor chip has a second upper surface and a second lower surface opposite thereto. The second semiconductor chip is disposed on the first semiconductor chip through conductive bumps disposed on the second lower surface and electrically connected to the bonding pads.

公开(公告)号：US20240006382A1

公开(公告)日：2024-01-04

申请号：US18311289

申请日：2023-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonjung Jang ,  Jungseok Ahn

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/481 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/293 ,  H01L24/81 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2225/06513

Abstract: The reliability of stacked semiconductor packages may be improved via a semiconductor package including a first semiconductor chip including through silicon vias (TSVs) with respective upper conductive pads electrically connected to the TSVs, a second semiconductor chip on the first semiconductor chip with lower conductive pads on a lower surface of the second semiconductor chip, conductive bumps between the upper conductive pads and the lower conductive pads, and an interlayer adhesive layer between the first semiconductor chip and the second semiconductor chip. An interlayer space is between the first semiconductor chip and the second semiconductor chip and overlaps the first semiconductor chip and the second semiconductor chip in a vertical direction. The encapsulant extends into the interlayer space.

公开(公告)号：US20230130983A1

公开(公告)日：2023-04-27

申请号：US17878355

申请日：2022-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyong Lee ,  Jungseok Ahn ,  Kuyoung Kim

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor device includes: a plurality of semiconductor chips stacked on a substrate in a vertical direction; a filler structure including a plurality of horizontal underfill layers formed between adjacent semiconductor chips of the plurality of semiconductor chips and between the substrate and the stack of semiconductor chips, and including underfill sidewalls formed around the horizontal underfill layers and the plurality of semiconductor chips; and a molding resin surrounding the plurality of semiconductor chips at least on side surfaces of the plurality of semiconductor chips. The underfill sidewalls include a recess pattern, which is disposed on and along the side surfaces of at least one of the plurality of semiconductor chips, and is recessed in a direction parallel to an upper surface of the substrate at locations where the recess pattern meets the substrate.