公开(公告)号：US10199497B2

公开(公告)日：2019-02-05

申请号：US15672767

申请日：2017-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooyeong Cho ,  Jaekyu Lee

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L29/78

Abstract: A semiconductor device includes an active pillar that protrudes above a substrate, the active pillar including a pair of vertical sections and a body interconnection between the pair of vertical sections, and each of the pair of vertical sections having a channel body and a lower impurity region below the channel body, word lines coupled to respective channel bodies, and buried bit lines in contact with respective lower impurity regions, wherein the channel bodies are connected to the substrate through the body interconnection.

公开(公告)号：US11087821B2

公开(公告)日：2021-08-10

申请号：US16367385

申请日：2019-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongpil Son ,  Wooyeong Cho

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408 ,  G06F3/06

Abstract: A memory module includes a plurality of memory devices each including a memory cell array, and a register clock driver connected to the memory devices. The register clock driver detects a row hammer address among row addresses corresponding to word lines of the memory cell array, converts a refresh command, among a plurality of refresh commands received from a memory controller for refreshing the memory cell array, to a row hammer refresh command, and transmits the row hammer refresh command and the row hammer address to each of the memory devices.

公开(公告)号：US20200090729A1

公开(公告)日：2020-03-19

申请号：US16367385

申请日：2019-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGPIL SON ,  Wooyeong Cho

IPC: G11C11/4076 ,  G11C11/406 ,  G11C11/408 ,  G06F3/06

Abstract: A memory module includes a plurality of memory devices each including a memory cell array, and a register clock driver connected to the memory devices. The register clock driver detects a row hammer address among row addresses corresponding to word lines of the memory cell array, converts a refresh command, among a plurality of refresh commands received from a memory controller for refreshing the memory cell array, to a row hammer refresh command, and transmits the row hammer refresh command and the row hammer address to each of the memory devices.

公开(公告)号：US20230073175A1

公开(公告)日：2023-03-09

申请号：US17929186

申请日：2022-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Korea Advanced Institute Of Science And Technology

Inventor： Daeshik Kim ,  Wooyeong Cho ,  Sanghyeok Son

IPC: G06T3/40 ,  G06N3/04 ,  G06V10/77 ,  G06V10/82

Abstract: Systems and methods for processing a plurality of images include obtaining input data including the plurality of images; providing the input data to a first machine learning model; providing an output of the first machine learning model to a second machine learning model and a third machine learning model; generating a first feature map corresponding to a plurality of kernels based on an output of the second machine learning model; generating a second feature map corresponding to a plurality of weights based on an output of the third machine learning model; generating a predicted kernel based on a weighted sum of the plurality of kernels; and generating output data based on the input data and the predicted kernel.

公开(公告)号：US10784311B2

公开(公告)日：2020-09-22

申请号：US16503937

申请日：2019-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mu-Hui Park ,  Wooyeong Cho

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/535

Abstract: A three-dimensional semiconductor memory device includes first to third cell array layers sequentially stacked on a substrate. Each of the first to third cell array layers includes memory cells arranged along first and second directions crossing each other and parallel to a top surface of the substrate. Each of the memory cells includes a variable resistance element and a tunnel field effect transistor connected in series. The device further includes bit lines extending along the first direction between the first and second cell array layers and at least one source line extending along either the first direction or the second direction between the second and third cell array layers. The memory cells of the first and second cell array layers share the bit lines, and the memory cells of the second and third cell array layers share the source line.

公开(公告)号：US10388699B2

公开(公告)日：2019-08-20

申请号：US15586307

申请日：2017-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mu-Hui Park ,  Wooyeong Cho

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/535

Abstract: A three-dimensional semiconductor memory device includes first to third cell array layers sequentially stacked on a substrate. Each of the first to third cell array layers includes memory cells arranged along first and second directions crossing each other and parallel to a top surface of the substrate. Each of the memory cells includes a variable resistance element and a tunnel field effect transistor connected in series. The device further includes bit lines extending along the first direction between the first and second cell array layers and at least one source line extending along either the first direction or the second direction between the second and third cell array layers. The memory cells of the first and second cell array layers share the bit lines, and the memory cells of the second and third cell array layers share the source line.