公开(公告)号：US20240379141A1

公开(公告)日：2024-11-14

申请号：US18781289

申请日：2024-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TONGSUNG KIM ,  YOUNGMIN JO ,  MANJAE YANG ,  CHIWEON YOON ,  JUNHA LEE ,  BYUNGHOON JEONG

IPC: G11C7/22 ,  G06F1/04 ,  G06F3/06 ,  G11C5/14 ,  G11C29/02

Abstract: A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. The first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.

公开(公告)号：US20220101895A1

公开(公告)日：2022-03-31

申请号：US17477931

申请日：2021-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGMIN JO ,  Byunghoon Jeong ,  TONGSUNG KIM ,  CHIWEON YOON ,  SEONKYOO LEE

IPC: G11C7/10

Abstract: A memory device includes a memory cell array, a page buffer, a control logic circuit, a plurality of input/output pins, a data bus inversion (DBI) pin, and an interface circuit. The page buffer is connected to the memory cell array. The control logic circuit is configured to control an operation of the memory cell array. The plurality of input/output pins receive a plurality of data signals from the controller. The DBI pin receives a DBI signal from the controller. The interface circuit count a first number of bits having a logic value of 1 and a second number of bits having a logic value of 0 from the data signals and the DBI signal and provide the data signals to the page buffer or the control logic circuit based on the first number and the second number.

公开(公告)号：US20220230666A1

公开(公告)日：2022-07-21

申请号：US17404510

申请日：2021-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TONGSUNG KIM ,  YOUNGMIN JO ,  MANJAE YANG ,  CHIWEON YOON ,  JUNHA LEE ,  BYUNGHOON JEONG

IPC: G11C7/22 ,  G06F3/06

Abstract: A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. The first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.

公开(公告)号：US20210133128A1

公开(公告)日：2021-05-06

申请号：US16853807

申请日：2020-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGMIN JO ,  DAESEOK BYEON ,  TONGSUNG KIM

IPC: G06F13/16 ,  G06N3/04 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device provides a first memory area and a second memory area. A smart buffer includes; a priority setting unit receiving sensing data and a corresponding weight, determining a priority of the sensing data based on the corresponding weight, and classifying the sensing data as first priority sensing data or second priority sensing data based on the priority, and a channel controller allocating a channel to a first channel group, allocating another channel to a second channel group, assigning the first channel group to process the first priority sensing data in relation to the first memory area, and assigning the second channel group to process the second priority sensing data in relation to the second memory area.

公开(公告)号：US20210365388A1

公开(公告)日：2021-11-25

申请号：US17118091

申请日：2020-12-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGMIN JO ,  DAESEOK BYEON ,  KISUNG KIM

IPC: G06F12/14 ,  G06F21/72 ,  G06F21/79 ,  G06F21/74 ,  G06F21/85 ,  H04L9/06

Abstract: A method of encrypting data in a nonvolatile memory device (NVM) includes; programming data in selected memory cells, sensing the selected memory cells at a first time during a develop period to provide random data, sensing the selected memory cells at a second time during the develop period to provide main data, encrypting the main data using the random data to generate encrypted main data, and outputting the encrypted main data to an external circuit, wherein the randomness of the random data is based on a threshold voltage distribution of the selected memory cells.

公开(公告)号：US20210132816A1

公开(公告)日：2021-05-06

申请号：US17027978

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGMIN JO ,  DAESEOK BYEON ,  TONGSUNG KIM

IPC: G06F3/06 ,  G06F12/02 ,  G06N3/08

Abstract: A memory device comprises a smart buffer, and a memory area divided into a first memory area and a second memory area, wherein the smart buffer comprises a priority setting unit configured to receive a sensing data and a corresponding weight from a controller, determine a priority of the sensing data based on the weight, and classify the sensing data as one of first priority sensing data and second priority sensing data, and a channel controller configured to allocate at least one channel selected from among a plurality of channels to a first channel group, allocate at least another channel selected from among the plurality of channels to a second channel group, assign the first channel group to process the first priority sensing data in relation to the first memory area, and assign the second channel group to process the second priority sensing data in relation to the second memory area, wherein a number of data input/output (I/O) pins connected to the first channel group is greater than a number of data I/O pins connected to the second channel group, wherein the memory area includes at least one memory chip, wherein the at least one memory chip includes a first chip having a first metal pad and a cell region and a second chip having a second metal pad and a peripheral circuit region, and the first chip and the second chip are vertically connected to each other by the first metal pad and the second metal pad.