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公开(公告)号：US11811364B2
公开(公告)日：2023-11-07
申请号：US17845378
申请日：2022-06-21
发明人： Jaehong Jung , Seunghyun Oh , Jinhyeon Lee , Gihyeok Ha , Seungjin Kim , Joomyoung Kim , Yelim Youn , Jaehoon Lee
CPC分类号： H03B5/32 , G06F1/06 , H03B5/04 , H03B5/20 , H03B2200/0082
摘要： A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.
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公开(公告)号：US20230288948A1
公开(公告)日：2023-09-14
申请号：US18103092
申请日：2023-01-30
发明人： Jaehoon Lee , Yelim Youn , Yong Lim
IPC分类号： G05F1/575
CPC分类号： G05F1/575
摘要： A hybrid low drop-out (LDO) regulator is provided. The hybrid LDO regulator provides current to a load block, and includes: an analog LDO regulator configured to provide a first current corresponding to an average current consumed by the load block; and a digital LDO regulator configured to provide a second current corresponding to a peak current consumed by the load block based on information indicating the peak current is consumed.
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