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公开(公告)号：US11916562B2
公开(公告)日：2024-02-27
申请号：US17673127
申请日：2022-02-16
发明人： Youngsea Cho , Wan Kim , Jiseon Paek , Seunghyun Oh
CPC分类号： H03M1/0617 , H03M1/38 , H03M1/66
摘要： A current steering digital-to-analog converter includes a plurality of current cells each including a current source circuit and a current switch circuit to selectively output a current in response to a first input signal corresponding to a digital signal; a dummy current cell including a dummy current source circuit and a dummy current switch circuit to output a current in response to a second input signal; and a current switch bias circuit coupled to the dummy current cell to track a first voltage of an internal node of the dummy current source circuit and configured to generate a first bias voltage applied to the current switch circuit.
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公开(公告)号：US11962311B2
公开(公告)日：2024-04-16
申请号：US17865811
申请日：2022-07-15
发明人： Gyusik Kim , Seungjin Kim , Seunghyun Oh
摘要： A sub-sampling phase locked loop includes a slope generating and sampling circuit, first and second transconductance circuits, a constant transconductance bias circuit, a loop filter and a voltage controlled oscillator. The slope generating and sampling circuit generates a sampling voltage based on a reference clock signal and an output clock signal. The first and second transconductance circuits generate first and second output control voltages based on the sampling voltage, a reference voltage and a control current. The constant transconductance bias circuit includes a switched capacitor resistor. The constant transconductance bias circuit is configured to generate the control current. The loop filter is connected to output terminals of the first and second transconductance circuits. The voltage controlled oscillator generates the output clock signal based on the first and second output control voltages.
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公开(公告)号：US11736115B2
公开(公告)日：2023-08-22
申请号：US17560400
申请日：2021-12-23
发明人： Youngsea Cho , Wan Kim , Jiseon Paek , Seunghyun Oh
CPC分类号： H03M1/466 , H03M1/1245
摘要： Provided are an analog-to-digital converter and/or an operating method thereof. The analog-to-digital converter includes a sample/hold circuit, a digital-to-analog converter, a comparing circuit, and a control logic circuit, wherein the digital-to-analog converter includes a first capacitor connected to a first comparison node and a first filtering node, a first reference voltage switch connected to the first filtering node and connected to a first delivery node or a first transmission node, a first pre-charge switch connected to the first filtering node or the first delivery node, and a first pre-charge capacitor connected to the first pre-charge switch and a ground voltage.
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公开(公告)号：US20220368337A1
公开(公告)日：2022-11-17
申请号：US17673127
申请日：2022-02-16
发明人： Youngsea CHO , Wan Kim , Jiseon Paek , Seunghyun Oh
IPC分类号： H03M1/06
摘要： A current steering digital-to-analog converter includes a plurality of current cells each including a current source circuit and a current switch circuit to selectively output a current in response to a first input signal corresponding to a digital signal; a dummy current cell including a dummy current source circuit and a dummy current switch circuit to output a current in response to a second input signal; and a current switch bias circuit coupled to the dummy current cell to track a first voltage of an internal node of the dummy current source circuit and configured to generate a first bias voltage applied to the current switch circuit.
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公开(公告)号：US11368125B2
公开(公告)日：2022-06-21
申请号：US17340593
申请日：2021-06-07
发明人： Jaehong Jung , Wonkang Kim , Seungjin Kim , Seunghyun Oh
摘要： A crystal oscillator reducing phase noise and a semiconductor chip including the same are provided. The crystal oscillator includes a transconductance circuit electrically connected to a crystal, a load capacitor connected to the transconductance circuit, a feedback resistance circuit connected between an input terminal of the transconductance circuit and an output terminal of the transconductance circuit, the feedback resistance circuit configured to provide a feedback resistance, and a variable resistance controller configured to generate a resistance control signal for controlling the feedback resistance, the resistance control signal causing the feedback resistance to have a first value in a first period and a second value in a second period, the first value being less than the second value, the first period corresponding to a first portion of a cycle of the clock signal, and the second period corresponding to a second portion of the cycle different from the first portion.
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公开(公告)号：US11183997B2
公开(公告)日：2021-11-23
申请号：US16855593
申请日：2020-04-22
发明人： Jaehoon Lee , Yong Lim , Wan Kim , Barosaim Sung , Seunghyun Oh
摘要： A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.
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公开(公告)号：US20210067150A1
公开(公告)日：2021-03-04
申请号：US16855593
申请日：2020-04-22
发明人： Jaehoon Lee , Yong Lim , Wan Kim , Barosaim Sung , Seunghyun Oh
摘要： A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.
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公开(公告)号：US11863240B2
公开(公告)日：2024-01-02
申请号：US16978651
申请日：2019-03-05
发明人： Dongil Yang , Seonjun Kim , Seunghyun Oh , Hanyeop Lee , Wonsub Lim , Hyoseok Na
CPC分类号： H04B17/103 , H04B1/401 , H04B17/10 , H04B17/102 , H04B17/12
摘要： The electronic device of the present invention may comprise: a first antenna and a second antenna; a communication circuit; and a processor electrically connected to the first antenna, the second antenna, and the communication circuit. The processor is configured to: control the communication circuit such that a first signal is output to the first antenna; acquire a second signal corresponding to the first signal reflected from the first antenna, and a third signal corresponding to the first signal output through the first antenna and received by the second antenna; identify a reflection coefficient at which the first signal is reflected from the first antenna, and a transmission coefficient at which the first signal is transmitted to the second antenna; and perform a designated function according to a value corresponding to a distance between the electronic device and an external object.
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公开(公告)号：US11811364B2
公开(公告)日：2023-11-07
申请号：US17845378
申请日：2022-06-21
发明人： Jaehong Jung , Seunghyun Oh , Jinhyeon Lee , Gihyeok Ha , Seungjin Kim , Joomyoung Kim , Yelim Youn , Jaehoon Lee
CPC分类号： H03B5/32 , G06F1/06 , H03B5/04 , H03B5/20 , H03B2200/0082
摘要： A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.
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10.发明授权公开(公告)号：US11777510B2
公开(公告)日：2023-10-03
申请号：US17964377
申请日：2022-10-12
发明人： Baekmin Lim , Seungjin Kim , Seunghyun Oh
CPC分类号： H03L7/1976 , H03L7/081 , H03L7/093
摘要： A fractional divider processing circuitry is to receive one of a plurality of clock signals as an input clock signal, and generate a first division clock signal based on the input clock signal and a first control signal. Phases of the plurality of clock signals partially overlap each other. The processing circuitry generates a delta-sigma modulation signal based on the first division clock signal and a frequency control word, and generates a second division clock signal based on the plurality of clock signals, the first division clock signal and a second control signal. The second control signal corresponds to a quantization noise of the delta-sigma modulation signal. The processing circuitry generates the second control signal and a digital control word based on the quantization noise of the delta-sigma modulator. The processing circuitry generates a final division clock signal based on the second division clock signal and the digital control word.
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