公开(公告)号：US20200033389A1

公开(公告)日：2020-01-30

申请号：US16272304

申请日：2019-02-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junbae KIM ,  Yongho CHO

IPC: G01R31/00 ,  G01R1/04 ,  G01R31/28 ,  G01R31/26

Abstract: A semiconductor device test system may include a body providing an internal space, in which a test device is loaded, and a cover coupled to the body to cover the internal space. The cover may include a first cover including first openings two-dimensionally arranged and a second cover including second openings two-dimensionally arranged. An arrangement of the first openings may be different from an arrangement of the second openings.

公开(公告)号：US20220121388A1

公开(公告)日：2022-04-21

申请号：US17394488

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungsuk WOO ,  Younguk CHANG ,  Yongho CHO

IPC: G06F3/06

Abstract: In a method of generating a signal for test in a memory device configured to output a multi-level signal, an operation mode is set to a first test mode. During the first test mode, first data bits included in a plurality of test data are arranged based on a first scheme. Each of the plurality of test data includes two or more data bits. During the first test mode, a first test result signal having two voltage levels is generated based on the first data bits according to the first scheme. The operation mode is set to a second test mode during which second data bits included in the plurality of test data are arranged based on a second scheme. During the second test mode, a second test result signal having the two voltage levels is generated based on the second data bits according to the second scheme.